Abstract: A programmable logic device integrated circuit incorporating a first-in, first-out memory block (250). First-in, first-out memory block (250) is coupled to a programmable interconnect array (213). Signals from the logic array blocks (LABs) (201) are connected to the control inputs of the first-in, first-out memory (250). In one embodiment, the programmable interconnect array (213) may be programmably coupled to the control inputs (259) of the first-in, first-out memory block. Status flag signals (276) from the first-in, first-out memory block (250) are programmably coupled to the programmable interconnect array (213). Data input (263) and data output (261) to first-in, first-out memory block (250) may be coupled to external, off-chip circuitry.