Abstract: A video graphics system employs a method and apparatus for improving throughput of the system. The video graphics system includes a graphics driver, a graphics processor, and a memory. Responsive to receiving a drawing command from an application, the graphics driver determines whether the graphics processor can begin executing the drawing command within a desired period of time. When the graphics processor is heavily loaded and cannot begin executing the command within the desired period of time, the graphics driver partially processes stored vertex information associated with the drawing command, and preferably stores the pre-processed vertex information in the memory. The graphics driver then preferably issues a new drawing command relating to the stored pre-processed information and instructing the graphics processor not to perform any of the processing already performed by the graphics driver. The graphics driver is preferably implemented in software and stored on a computer-readable storage medium.

Abstract: A method and apparatus for determining a rear most Z value for a pixel block is presented, where the pixel block is a portion of the image data for a frame as stored in a frame buffer. The frame buffer is stored in a DRAM memory structure that is included on an integrated circuit along with a render backend block that blends received fragments from a three-dimensional (3D) video graphics pipeline with the image data stored in the frame buffer. The 3D video graphics pipeline is located on a video graphics processing integrated circuit separate from the integrated circuit storing the frame buffer and render backend block. The integrated circuit storing the frame buffer includes a value determination block that determines the rear most Z value. The value determination block includes a data serialization block that serializes the bits corresponding to the Z values for the pixels included in the pixel block to produce a plurality of corresponding serial bit streams.

Abstract: A system includes a main memory device which stores information for translating a virtual address into a physical address in response to one of a plurality of processing devices. A memory control/interface device is coupled to the main memory device. The memory control/interface device, which may access the information stored in the main memory device, has a separate translation look-aside buffer for each processing device. Each translation look-aside buffer can buffer the information for use in translating in response to the respective processing device.

Abstract: Methods and apparatus are provided for allocating correlated data sets, such as texture data, among first and second areas of memory in a computer graphics system. Each texture map in a series of texture maps is divided into a set of blocks of data. Each texture map that has a width greater than one block is divided into first and second map areas. Typically, the first and second map areas are the left and right halves of each texture map. Blocks of data from the first map areas of odd level texture maps are stored in the first memory area, blocks of data from the second map areas of even level texture maps are stored in the first memory area, blocks of data from the second map areas of odd level texture maps are stored in the second memory area and blocks of data from the first map areas of even level texture maps are stored in the second memory area. The blocks of data representing each texture map in the series of texture maps are stored in consecutive blocks of memory.

Abstract: In one embodiment, the invention is a method. The method includes monitoring a data stream. The method also includes partitioning a cache into two sub-caches based on monitoring the data stream.