Abstract: Processes and fixtures for producing electromechanical devices, and particularly three-dimensional electromechanical devices such as inertial measurement units (IMUs), through the use of a fabrication process and a three-dimensional assembly process that entail joining single-axis device-IC chips while positioned within a mounting fixture that maintains the orientations and relative positions of the chips during the joining operation.

Abstract: Silicon on insulator structures having a high resistivity region in the handle wafer of the silicon on insulator structure are disclosed. Methods for producing such silicon on insulator structures are also provided. Exemplary methods involve creating a non-uniform thermal donor profile and/or modifying the dopant profile of the handle wafer to create a new resistivity profile in the handle wafer. Methods may involve one or more SOI manufacturing steps or electronic device (e.g., RF device) manufacturing steps.

Abstract: A diode laser having aluminum-containing layers and a Bragg grating for stabilizing the emission wavelength achieves an improved output/efficiency. The growth process is divided into two steps for introducing the Bragg grating, wherein a continuous aluminum-free layer and an aluminum-free mask layer are continuously deposited after the first growth process such that the aluminum-containing layer is completely covered by the continuous aluminum-free layer. Structuring is performed outside the reactor without unwanted oxidation of the aluminum-containing semiconductor layer. Subsequently, the pre-structured semiconductor surface is further etched inside the reactor and the structuring is impressed into the aluminum-containing layer.

Abstract: A MEMS microphone system suited for harsh environments. The system uses an integrated circuit package. A first, solid metal lid covers one face of a ceramic package base that includes a cavity, forming an acoustic chamber. The base includes an aperture through the opposing face of the base for receiving audio signals into the chamber. A MEMS microphone is attached within the chamber about the aperture. A filter covers the aperture opening in the opposing face of the base to prevent contaminants from entering the acoustic chamber. A second metal lid encloses the opposing face of the base and may attach the filter to this face of the base. The lids are electrically connected with vias forming a radio frequency interference shield. The ceramic base material is thermally matched to the silicon microphone material to allow operation over an extended temperature range.

Abstract: A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.

Abstract: A method for forming a split gate device includes forming a first sidewall of a first conductive gate layer, wherein the semiconductor layer includes a tunnel region laterally adjacent the first sidewall, forming a dielectric layer along the first sidewall to provide for increased thickness of a gap spacer, forming a charge storage layer over a portion of a top surface of the first conductive layer and over the tunnel region, and forming a second conductive gate layer over the charge storage layer.

Abstract: A method of manufacturing an isolation structure includes forming a laminate structure on a substrate. A plurality trenches is formed in the laminate structure. Subsequently a pre-processing is effected to form a hydrophilic thin film having oxygen ions on the inner wall of the trenches. Spin-on-dielectric (SOD) materials are filled into the trenches. The hydrophilic think film having oxygen ions changes the surface tension of the inner wall of the trenches and increases SOD material fluidity.

Abstract: A semiconductor device includes a vertical semiconductor element having a super junction structure constructed of a first conductivity-type drift layer disposed on a surface of a semiconductor substrate and second conductivity-type regions having a stripe shape defining a longitudinal direction in one direction and being arranged at a predetermined column pitch in the drift layer. When a surplus concentration obtained by dividing a difference between an electrical charge of the second conductivity-type region and an electrical charge of a first conductivity-type region by the column pitch is i, a depth of the super junction structure is z, a surplus concentration gradient as a change of the surplus concentration i per unit depth dz is di/dz, and a central withstand voltage in which a margin is added to a desired withstand voltage is Vmax, the super junction structure is configured such that the surplus concentration gradient di/dz satisfies a relation of 0 > ? i ? z > - ( 7.

Abstract: A salicide process is described. A substrate having thereon an insulating layer and a silicon-based region is provided. A nickel-containing metal layer is formed on the substrate. A first anneal process is performed to form a nickel-rich silicide layer on the silicon-based region. The remaining nickel-containing metal layer is stripped. A thermal recovery process is performed at a temperature of 150-250° C. for a period longer than 5 minutes. A second anneal process is performed to change the phase of the nickel-rich silicide layer and form a low-resistivity mononickel silicide layer.

Abstract: A semiconductor device includes: a semiconductor substrate having a hexagonal crystalline structure with a c-axis and c-planes; and transistors on a c plane of the semiconductor substrate. Source electrodes of the transistors are connected to each other. Drain electrodes of the transistors are connected to each other. Gate electrodes of the transistors are connected to each other. The gate electrodes of the transistors extend along directions that form angles with each other that are 60 degrees or 120 degrees, in a plan view seen from a direction perpendicular to the c plane of the semiconductor substrate.

Abstract: A device (10) may include a semiconductor layer section (25) and a memory layer section (45) disposed above the semiconductor layer section (25). The semiconductor layer section (25) may include a processor (12; 412) and input/output block (16; 416), and the memory layer section (45) may include memristive memory (14; 300). A method of forming such device (10), and an apparatus (600) including such device (10) are also disclosed. Other embodiments are described and claimed.

Abstract: A curable organopolysiloxane composition in grease or paste form, which including: (A) an organopolysiloxane having at least two alkenyl groups bonded to silicon atom in one molecule; (B) an organohydrogenpolysiloxane having at least two hydrogen atoms bonded to silicone atom in the molecule; (C) gallium and/or a gallium alloy having a melting point of 0 to 70° C.; (D) a thermally conductive filler having an average particle size of 0.1 to 100 ?m; (E) a platinum-based catalyst; and (F) a polysiloxane of the following general formula (1): wherein R1 may be the same or different and represents a monovalent hydrocarbon group, R2 represents an alkyl group, an alkoxyl group, an alkenyl group or an acyl group, a is an integer of 5 to 100, and b is an integer of 1 to 3.

Abstract: A method includes bonding a first bond layer to a second bond layer through eutectic bonding. The step of bonding includes heating the first bond layer and the second bond layer to a temperature higher than a eutectic temperature of the first bond layer and the second bond layer, and performing a pumping cycle. The pumping cycle includes applying a first force to press the first bond layer and the second bond layer against each other. After the step of applying the first force, a second force lower than the first force is applied to press the first bond layer and the second bond layer against each other. After the step of applying the second force, a third force higher than the second force is applied to press the first bond layer and the second bond layer against each other.

Abstract: An extremely non-degenerate two photon absorption (END-2PA) method and apparatus provide for irradiating a semiconductor material substrate simultaneously with two photons each of different energy less than a bandgap energy of the semiconductor material substrate but in an aggregate greater than the bandgap energy of the semiconductor material substrate. A ratio of a higher energy photon energy to a lower energy photon energy is at least about 3.0. Alternatively, or as an adjunct, the higher energy photon has an energy at least about 75% of the bandgap energy and the lower energy photon has an energy no greater than about 25% of the bandgap energy.

Abstract: In an embodiment of the invention, a method of fabricating a floating-gate NMOSFET (n-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves as the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.

Abstract: According to one embodiment, a method for manufacturing a semiconductor light emitting device includes: preparing a metal plate including first frames and second frames, the first frames and the second frames being alternately arranged and spaced from each other, a light emitting element being fixed to each of the first frames, the light emitting element being connected to an adjacent one of the second frames via a metal wire; molding a first resin on the metal plate, the first resin covering the first frame, the second frame, and the light emitting element; forming in the first resin a groove defining a resin package including the first frame, the second frame, and the light emitting element; filling a second resin inside the groove; and forming the resin package with an outer edge of the first resin covered with the second resin by cutting the second resin along the groove.

Abstract: A break on a video signal line is prevented during patterning on the video signal line. A video signal line, a drain electrode, and a source electrode are simultaneously formed in the same layer. The video signal line includes three layers: a base layer, an AlSi layer, and a cap layer. Conventionally, an alloy having a high etching rate is formed at the boundary between the AlSi layer and the cap layer, causing breakage during patterning on the video signal line. According to the present invention, in the formation of the video signal line, the AlSi layer is formed by sputtering, a TFT is exposed to the atmosphere to form an Al oxide layer on the surface of the AlSi layer, and then the cap layer is formed by sputtering. Thus, the formation of an alloy having a high etching rate on a part of the AlSi layer is prevented, precluding the occurrence of a break on the video signal line.

Abstract: So as to manufacture an intrinsic absorber layer of amorphous hydrogenated silicon within a p-i-n configuration a solar cell by PeCvD deposition upon a base structure, thereby improving throughput an simultaneously maintaining quality of the absorber layer, a specific processing regime is proposed, wherein in the reactor for depositing the addressed absorber layer a pressure of between 1 mbar and 1.8 mbar is established and a flow of silane and of hydrogen with a dilution of silane to hydrogen of 1:4 up to 1:10 and generating an RF plasma with a generator power of between 600 W and 1200 W per 1.4 m2 base structure surface to be coated.

Abstract: In a semiconductor wafer with a supporting tape attached to the back side of the wafer, a coating member having a refractive index close to that of the supporting tape is formed on a pear-skin surface of the supporting tape to thereby planarize the pear-skin surface. Thereafter, a pulsed laser beam is applied from the upper side of the coating member to the semiconductor wafer in the condition where the focal point of the pulsed laser beam is set at a predetermined depth in the semiconductor wafer. Accordingly, the pulsed laser beam can be sufficiently focused inside the semiconductor wafer to thereby well form a modified layer inside the semiconductor wafer.

Abstract: A method of forming a semiconductor device. A substrate having first and second materials is provided, wherein the second material is occluded by the first material. The substrate is etched using a first non-plasma etch process that etches the first material at a higher rate relative to a rate of etching the second material. The first non-plasma etch process exposes the second material that is overlying at least a portion of the first material. The second material is then etched using a plasma containing a reactive gas, which exposes the at least a portion of the first material. The first material including the at least a portion of the first material that was exposed by etching the second material are etched using a second non-plasma etch process.