Abstract: A semiconductor device comprises first and second island regions of a first conductivity type formed closely to each other in the surface area of a semiconductor substrate, first-and second-channel type MOS FETs formed in the first island region, and a high impurity concentration region of the first conductivity type having an impurity concentration higher than the island regions and formed between the substrate and at least one of the first and second island regions, the high impurity concentration region being formed to surround the island regions.

Abstract: The invention is directed to a semiconductor nonvolatile memory of the floating gate type having dual gate structure comprised of a first channel region having a channel resistance controlled by a control gate electrode and a second channel region having a channel resistance controlled by a floating gate electrode. The first channel region is formed on one face section of semiconductor substrate which has a crystal face orientation different from that of another face section on which the second channel region is formed. By such construction, channel length of the first and second channel regions can be shortened to increase memory capacity density and to improve quality.

Abstract: A device comprising semiconductor elements and conductor tracks of an oxidic superconductive material, electrically conductive connections being established between the semiconductor elements and the conductor tracks, is provided with an electrically conductive antidiffusion layer between the semiconductor elements and the conductor tracks. The antidiffusion layer consists of an amorphous alloy of two transition metals, which alloy has a crystallization temperature of at least 900 K. The amorphous alloy has the composition A.sub.x B.sub.1-x, wherein A is selected from Ti, Zr, Hf, Nb and Ta, wherein B is selected from Ir, Pd and Pt, and wherein x has a value from 0.4 to 0.8.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a semiconductor integrated circuit including the semiconductor substrate, a semiconductor chip having the semiconductor substrate and semiconductor integrated circuit, and a plurality of substrate bias generation circuits arranged on the semiconductor chip in such a manner as to derive substrate bias voltages from a power source voltage supplied from the exterior to the semiconductor chip and uniformly apply the substrate bias voltages over the entire the semicondutor substrate.

Abstract: A SOI-MOSFET formed on a thin semiconductor layer (3) having a thickness not more than 1500.ANG. includes a charge carrier absorbing region (9a, 9b, 9c) contacting with at least a portion of the bottom of a channel region (6) of a first conductivity type and with at least a portion of the bottom of a source region (7, 7a) of a second conductivity type. The carrier absorbing region (9a, 9b, 9c) absorbs excess carriers of the first conductivity type contained in the channel region (6).

Abstract: Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, ohmic contacts to the source and drain regions, and a p-n junction contact to each of the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two p-n junction contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the p-n junction diodes. Minority carriers injected by the diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device.

Abstract: Single package, electrically isolated dual, triple, quad, etc., power semiconductor devices are provided without use of ceramic or other isolators between the semiconductor die and the die support. For example, isolated dual power transistors, each having three leads, are encapsulated within the same package outline and lead footprint as a seven lead TO-218 or TO-220 by dividing the die flag into two spaced-apart portions, one for each die, connecting the first three leads to the first transistor and die flag, connecting the last three leads to the second transistor and die flag, and omitting the centrally located fourth lead. The spaced-apart die flags and leads are supported by a molded encapsulation.

Abstract: A variable-capacitance diode element is disclosed which comprises a semiconductor substrate of a first conductivity type having an epitaxial layer of the first conductvity type provided on a main surface portion thereof, said epitaxial layer having a higher resistivity than that of said semiconductor substrate; a first diffusion layer of the first conductivity type diffused in said epitaxial layer and having a lower resistivity than that of said epitaxial layer; a second diffusion layer of a second conductivity type surrounded by said first diffusion layer and having a lower resistivity than that of said first diffusion layer; and a third diffusion layer of the second conductivity type of a small diffusion length covering an exposed portion of a major surface of said first diffusion layer and an exposed portion of a major surface of said diffusion layer. With such construction, the capacitance variation range of the diode element is widened, and the high-frequency serial resistance R.sub.

Abstract: An integrated circuit includes a memory having cells arranged in rows and columns, each cell having transistor being connected between two bit lines and having a current channel, a control gate and a charge-storage region therebetween, neighboring cells in a same row having a bit line contact in common, and control gates of transistors in a row being connected to a same word line, wherein each transistor has in a substrate of a first conductivity type a source region, a drain region and an injector region of a second conductivity type and mutually separated from each other, the injector regions of the transistors in a first row being controllable via the bit line contacts of the transistors in a second row adjacent to said first row. Preferably, at least one source region, at least one drain region and at least one injector region that are connected to a same bit line contact form a coherent region, e.g. a well, in the substrate. Preferably, the first and second row have the word line in common.

Abstract: The present invention relates to an integrated circuit which includes complementary MOS transistors (e.g., a CMOS circuit), an EEPROM, and to a method of making the integrated circuit. The EEPROM is incorporated in the circuit in such a manner that it does not adversely affect the high performance, low voltage operation of the CMOS circuit. Also, the EEPROM is designed so that it is programmable at a low voltage which is compatible with the low voltages typically used with the CMOS circuit. The EEPROM includes a floating gate and a control gate which have a large area of overlap so as to provide a high capacitance therebetween. This provides a high ratio (e.g., about two or greater) of the floating gate to control gate capacitance divided by the floating gate to substrate capacitance to provide the EEPROM with the low voltage operation. To make the integrated circuit, standard CMOS process steps using design rules of about two microns or less are used to make the MOS transistors.

Abstract: The present invention provides a linear resistance element comprising a p of transistors. The transistor pair includes first and second depletion-type field effect transistors each having a gate, a source electrode, a drain electrode, a channel mobility, and a threshold voltage. The source and drain electrodes of each transistor define a source-drain current path through a channel. The first and second transistors are connected with their source-drain paths in series with each other. The gates of the first and second transistors are connected in common to the series connection between the source-drain current paths. The channel width-to-length ratio, channel mobility, and threshold voltage of the first transistor are substantially equal to the corresponding properties of the second transistor. Any number of transistor pairs may be serially connected together.

Abstract: A protection structure comprises a semiconductor substrate of a first conductivity type with a region of second conductivity type in the substrate at the surface thereof. A region of second conductivity type has disposed therein first and second regions of the second conductivity type, a third region of the first conductivity type adjacent the surface of the substrate, and a fourth region of the second conductivity type adjacent the substrate surface adjacent the third region. A shallow field region extends a distance into the region of second conductivity type between the first and second regions. A first electrical contact overlies the surface of the first region and a second electrical contact overlies the third and fourth regions.

Abstract: A vertical MOSFET device including a semiconductor layer having a first conductivity type, in which a base region having a second conductivity type is formed in the semiconductor layer, and a source region having the first conductivity type is formed in the base region, in which a gate electrode is formed at least on the above described base region via an insulating gate film to form a channel between the semiconductor layer and the source region, and a protector having PN or Schottky junction, which is formed between the source region and the gate electrode and is thermally contacted with at least one of the other members.

Abstract: The electrode structure for selectively energizing a particular light emitting diode site of a light emitting diode array chip includes a narrow electrode strip connected at one end to the diode site, a test pad wider than the conductor strip electrically connected to the other end thereof, a bonding pad wider than said electrode strip and spaced from the test pad opposite the diode site and a severable connecting strip narrower than either pad electrically connecting those two pads to each other.