Abstract: A slave processor adapted to execute a read/write operation in response to a read/write request signal from a master processor, comprises a first circuit for performing a write operation during a predetermined period of time from the moment a first write request signal is made inactive from an active condition. An second circuit is provided for generating, when another access request signal such as a second write request signal or a read request signal is made active during the above predetermined period of time, an active wait signal requiring the master processor to maintain the second access request signal in an active condition. The second circuit also operates to delay an operation indicated by the second access request signal.

Abstract: An interface circuit can assign a common input/output port address to a plurality of I/O circuits. Each common I/O port is defined in terms of pages. In an actual data input/output, a specific port address is used for port control so as to select one common page. The interface circuit has a first decoder for decoding a specific port address signal. The interface circuit also had a data setter for setting data supplied from a specific bit line of the data bus. The data is set in the data setter in accordance with the decoded signal from the first decoder. Each of the plurality of I/O circuits has a second decoder for decoding the common I/O port address signal. An output from the setter enables a corresponding one of second decoders. As a result, a specific page is selected.

Abstract: A high performance terminal input/output subsystem for connecting a multiplicity of user devices to a multi-user computer includes a single-board host adapter which is mounted in a single bus slot in the host computer card cage and provides the communication between the subsystem and the host computer. One or more multiple terminal, intelligent cluster controllers is remotely located from and coupled to the host adapter by means of a coaxial cable. The cluster controllers are multidropped from the coaxial cable in daisy chain fashion. Communication between the host adapter and cluster controllers utilizes a high speed communication line employing a 2.5 Mbit/second baseband, token-passing, serial bus, local area network protocol. Each cluster controller provides local terminal connections for 8 or 16 user devices.

Abstract: A word processor includes a work station having a keyboard and a display device, a main unit for forming a text file in accordance with input commands entered by the keyboard, an external memory unit for storing the text file, a standardized character memory for storing dot patterns of characters having standardized style, a modified character memory for storing dot patterns of characters having modified style, and a printer for printing out a document in accordance with the text file. When a plurality of documents to be delivered to different addresses are formed in accordance with the same text file, different characters in respective documents are replaced by modified characters to form text files having different modified characters. Then the plurality of documents are printed in accordance with respective text files having different modified characters, so that these documents can be distinguished from one another.

Abstract: An I/O interface (24) couples a plurality of I/O devices (29) to a main memory (22) by way of a system bus (23). The I/O interface includes a plurality of buffer blocks (110) permanently associated with one or more memory pages (240). Each page is contiguous within the memory address spectrum and includes a plurality of memory blocks (230). Under control of a sequencer (125), the buffer blocks temporarily store data items being transferred between the memory and the devices. Data items being transferred between any and all devices and a particular memory page are temporarily stored by that page's associated buffer block and no other buffer block. The sequencer accumulates in a buffer block a plurality of data items being transferred by a device to memory by successive write requests, and causes a direct memory access (DMA) conveyance of the buffer contents to the memory upon occurrence of any one of a number of events.

Abstract: The present invention consists of a hardware simulator with bus evaluator logic for use in simulating and fault grading of very large scale digital circuits containing buses. In this invention the status of a bus is continously upgraded each time a primitive is evaluated that has an output coupled to the bus. As bus driver primitives are evaluated, the state of the bus is determined on the fly and stored in an accumulator register, called the bus register. Evaluation of the bus continues using the data stored in the bus register and the state of each driver until all drivers have been evaluated. After the last bus driver is evaluated the state of the bus is known and the bus primitive is assigned the value, or state, stored in the bus register hardware and is passed to all receivers on the bus.

Abstract: An apparatus for use with a DMA controller includes a device interface controller having therein both general and specific command programs, and device bus interface. The apparatus is arranged to intercept all communication signals between the DMA controller and a microcomputer associated therewith.

Abstract: A method for the intelligent, in-line, dynamic editing of documents containing mixed object types on a computer work station is disclosed. The mixed object types may be text objects, draw graphics objects, business graphics objects, and tables objects. The editor executes actions on use selected objects and attributes based on internal knowledge of the object type selected rather than by explicit user commands. This procedure provides a simple user interface that makes manipulation of objects and attributes and command execution transparent to the user.

Abstract: A queue state access protocol device for serial exchange of numerical information among terminals interconnected by an optical fiber star network, transmits queue state data over a small fraction of the network's total information channel capacity. A circuit measures the distance from each terminal to the star center and allows the terminals to synchronize their respective queue state transmissions, thereby minimizing the physical occupation of transmission channels. The delay queue for accessing the network is managed by a microprocessor which is provided in each terminal of the network.

Abstract: The electronic circuit connects a processor to a high-capacity memory of 1 Megabyte. The processor may be of the 8 bit type, with a 16 bit address bus (A0-A15). The memory is subdivided into 256 segments each having a capacity of 4 Kbytes which can be directly addressed by the processor by means of 12 (A0-A11) of the 16 lines of the address bus. An auxiliary RAM is interposed between the processor and has 1 Mbyte memory and comprises sixteen 8 bit registers (R0-R15), which can be addressed by means of the other four lines (A12-A15), of the address bus. By means of the 8 bit data bus (D0-D7), the 16 registers of the RAM store the numbers of those 16 segments out of the 256 segments of the 1 Mbyte memory, which from time to time are connected to the processor. In this way the processor, while being able to address only 64 Kbytes of memory at a time, has the whole of the 1 Mbyte memory available. The circuit can be applied to data processing and word processing units and electronic typewriters.

Abstract: An operator interactive translation system for translating sentences in a first language to sentences in a second language includes a separate memory for storing translated words in the second language as learned words corresponding to input words in the first language, upon being indicated as correct equivalents by the user. For each subsequent translation using sentence construction and morpheme analysis, the learned word stored in the buffer memory is selected as the first translation each time the specific input word in the first language appears in a sentence to be translated.

Abstract: A word-processing system or memory typewriter has the usual keyboard, input display and/or printer; together with a spelling dictionary stored within the memory, and an error signal generating device activated upon entry of an incorrect word. For greater efficiency and ease of use by the operator, the memory also stores several kinds of correction information--e.g., typographical correction, transposition reversal, phonetic substitutions, etc.--suitable for amending the incorrect word to display a trial word which matches one from the above-mentioned stored dictionary, the amending occurring by depression of a special key whenever entry of an incorrect word activates the error-signal device. Statistical control of selection of the class of correction information is provided, the order of utilization of the various classes depending upon the relative extent of the operator's prior successful usage of each class of information.

Abstract: A data processing system includes a plurality of data processing modules coupled to a bus and to a set of control lines. These modules request the use of the bus by sending respective sequences of at least two binary numbers during successive cycles on the control lines in synchronization with each other. On the control lines the numbers are logically ORed together. Each module terminates the sending of its numbers if, during any one of the successive cycles, the logical OR is greater than twice the number which the module itself is sending. A module uses the bus only if, during each of the successive cycles, the logical OR does not exceed the number which the module itself sends.

Abstract: A logic simulator for simulating operation of a logic circuit is provided with gates divisible into successive levels according to a connection pattern between the gates. A pattern memory (16) memorizes the connection pattern as a bit sequence representative of direct connections between each gate of each level to the gates of a preceding level. A function memory (17) memorizes logic functions of the respective gates. Responsive to input logic states of each level, the bit sequence for the gates of the level under consideration, and the logic functions of the respective gates of that level, a calculator (25) calculates output logic states of that level as input logic states of a succeeding level successively for the gates of the level in question. For a higher speed of simulation, the logic circuitry may be divided into a predetermined number of gate groups, each consisting of gates of the successive levels. Each of the pattern and the function memories is divided into parts for the respective gate groups.

Abstract: In a processor such as a vector processor in which a plurality of data are processed by one instruction and a plurality of instructions are parallely processed, apparatus is provided for storing, during an interruption of the program currently being executed, the instructions being executed in the conceptual order of appearance in the program of the instruction being executed, and the sequential count of the sets of data processed. The stored information is used to restart the execution of the interrupted program at the appropriate point.

Abstract: A parallel processing computer comprises at least a memory for storing program as well as data and instructions for executing the program, a plurality of functional units, a node driving register for indicating executable instructions which are allowed to be executed by the functional units, and a mode register giving information to the functional unit as to whether the processing to be executed is of serial nature or parallel nature.

Abstract: An arbitration system for a machine tool control has multiple processors and a local memory associated with each processor. The arbitration system allows one processor to access data stored in a foreign memory, i.e. the local memory of a second processor so that the time required for one processor to gain access to data used by another processor is relatively short. The system includes an external arbitration control which arbitrates requests for access to a foreign memory from each of the processors. The system also includes a plurality of local arbitrators each associated with a particular processor to arbitrate requests for access to its processor's bus and memory from a plurality of users including the external arbitration control, a DRAM controller and a direct memory access controller.

Abstract: A data transfer network includes a group of disk drive peripheral units, each has dual ports for connection to two separate peripheral-controllers. A host computer can initiate either peripheral-controller to access selected disk drive units for Read/Write operations.

Abstract: A silicon semiconductor wafer containing a plurality of silicon integrated circuits formed therein or attached thereto contains at least one data bus to which some of the circuits are connected. Each of the circuits coupled to the data bus contains an arbitration request circuit which selectively passes a signal that requests that its circuit be given access to the data bus so it can transmit information to another circuit on the wafer. In addition, each of the circuits coupled to the data bus has an arbitration circuit which detects which of any of the circuits coupled to the data bus is requesting access to the data bus and facilitates its circuit gaining access to the data bus if its circuit has a higher preselected priority than any other circuit which is simultaneously seeking access to the data bus. The distribution of the arbitration request circuits and of the arbitration circuits simplifies layout and tends to improve the speed of operation.