Abstract: An interrupt controller circuit arrangement is used for encoding and storing "interrupt" signals indicating random (asynchronous) occurrence of corresponding events and for delivering corresponding "interrupt" (alarm command) signals to a (synchronous) microprocessor corresponding to the events as they occur. The events are divided into two (or more) sets in order to reduce the required number of latches and to increase the speed of operation. One (or more) of these sets consists of events which never can occur "simultaneously" (i.e., which are mutually exclusive in the sense that (within each of such sets) not more than a single one of the events can occur--and can occur only once--within a prescribed amount of time); the remaining set consists of the remaining events--i.e., those which can occur "simultaneously" or can occur simultaneously with one or more of those in the other set(s).

Abstract: A multi-processing device includes three or more processing systems, each having a processor and a corresponding main memory connected to each other by means of an individual memory bus. The multi-processing device also includes a common memory bus connectable to all the processors and all the main memories of the respective systems, an asynchronism detection circuit connected to the respective processors to produce an asynchronism detection signal indicating which system or systems are in asynchronous state, and a device control circuit responsive to the asynchronism detection signal to send a common memory bus select signal to the main memory of each failed system to change its bus connection from the individual memory bus to the common memory bus. The device control circuit also generates a master designation signal for allowing an arbitrary processor of the normal non-faulty systems to be designated as a master processor, and a copy request signal to the respective processors.