Patents Examined by Daniel A Dersarkissian
  • Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor
    Patent number: 8924695
    Abstract: An architectural instruction instructs a microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result, determines whether the architectural condition flags satisfy the condition, and updates a non-architectural indicator to indicate whether the architectural condition flags satisfy the condition.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: December 30, 2014
    Assignee: Via Technologies, Inc.
    Inventors: G. Glenn Henry, Gerard M. Col, Rodney E. Hooker, Terry Parks
  • Garbage collection implemented in hardware
    Patent number: 8856491
    Abstract: A computing device is provided and includes a memory module, a sweep engine, a root snapshot module, and a trace engine. The memory module has a memory implemented as at least one hardware circuit. The memory module uses a dual-ported memory configuration. The sweep engine includes a stack pointer. The sweep engine is configured to send a garbage collection signal if the stack pointer falls below a specified level. The sweep engine is in communication with the memory module to reclaim memory. The root snapshot engine is configured to take a snapshot of roots from at least one mutator if the garbage collection signal is received from the sweep engine. The trace engine receives roots from the root snapshot engine and is in communication with the memory module to receive data.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: David F. Bacon, Perry S. Cheng, Sunil K. Shukla
  • Methods, systems and computer readable medium for writing and reading data
    Patent number: 8838937
    Abstract: A flash memory controller, a computer readable medium and a method for writing to a flash memory device, the method may include receiving multiple logical pages, each logical page having a logical address; determining to write a logical page into a selected physical page of the flash memory device; calculating a hash value for each logical page of the multiple logical pages in response to (a) a logical address of the logical page and (b) a physical page index, to provide multiple hash values of the multiple logical pages.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: September 16, 2014
    Assignee: Densbits Technologies Ltd.
    Inventors: Michael Katz, Hanan Weingarten