Abstract: This patent describes a method of manufacturing a thermoelastic rotary impeller ink jet print head wherein an array of nozzles are formed on a substrate utilizing planar monolithic deposition, lithographic and etching processes. Multiple ink jet heads are formed simultaneously on a single planar substrate such as a silicon wafer. The print heads can be formed utilizing standard VLSI/ULSI processing and can include integrated drive electronics formed on the same substrate. The drive electronics preferably being of a CMOS type. In the final construction, ink can be ejected from the substrate substantially normal to the substrate plane.

Abstract: A method is shown for producing a PIN photodiode wherein an intrinsic layer of the photodiode can be made arbitrarily thin. A fabrication substrate is lightly doped to have a first conductivity type in order to form the intrinsic layer of the photodiode. A first active region of the photodiode having the first conductivity type is formed on a first surface of the fabrication substrate. An oxide layer is also formed upon the first surface of the fabrication substrate. A handling substrate is bonded to the first surface of the fabrication substrate. A second surface of the fabrication is then lapped to a obtain a preselected thickness of the intrinsic layer. And a second active region of the photodiode having a second conductivity type is formed on the second surface of the fabrication substrate.

Abstract: The present invention provides an improved ferroelectric capacitor used in a memory device by providing reliable electrical interconnection between a lower electrode of the capacitor and an active region of transistor, and to provide a method for fabricating the same. A semiconductor capacitor according to the present invention comprises: a first conducting film filling an opening which is formed in an interlayer insulating film, being in contact with an active region of a semiconductor; a stacked charge storage node including a second conducting film formed on the first conducting film and an interlayer insulating film, a first diffusion preventing film formed on the second conducting film, a lower electrode film formed on the first diffusion preventing film, and a ferroelectric film formed on the lower electrode film; and a conducting spacer film formed on sidewalls of the lower electrode film, the first diffusion preventing film and the second conducting film.

Abstract: In a method of a semiconductor device, an insulating film on a semiconductor substrate is formed. Then, a first mask on the insulating film in a first region is formed and the insulating film is removed using the first mask for isolation insulating films in the first region. In this case, an element to be formed in the first region has a first active region. Also, a second mask is formed on the insulating film in a second region. The second mask is different from the first mask. The insulting film is removed using the second mask for isolation insulating films in the second region. In this case, a first element to be formed in the first region has a first active region narrower than a second active region of a second element to be formed in the second region. Generally, the insulating film in the first region is removed and then the insulating film in the second region is removed.

Abstract: A silicon nitride film and a silicon oxide film are deposited in that order on a WSi film. In a single session of lithography, the gate electrode of a memory cell and the gate electrode of a transistor constituting a peripheral circuit are formed. The silicon oxide film makes a mask used to form a floating gate of the memory cell. The silicon nitride film makes a mask used to form a common source region by etching a gate oxide film and a field oxide film. The silicon nitride film covers the WSi film to prevent impurities from entering the WSi film when impurities are introduced into the common source region. This prevents abnormal oxidation in a subsequent process.

Abstract: A trench capacitor having a diffusion region adjacent to the collar to increase the gate threshold voltage of the parasitic MOSFET. This enables the use of a thinner collar while still achieving a leakage that is acceptable. In one embodiment, the diffusion region is self-aligned.

Abstract: A new method of local oxidation using nitrogen implant to reduce the growth of a bird's beak is described. An oxide layer is provided over the surface of a semiconductor substrate. A first silicon nitride layer is deposited overlying the oxide layer. An opening is etched through the first silicon nitride layer to the oxide layer where the device isolation region is to be formed. Nitrogen ions are implanted through the oxide layer to form a nitrogen implanted area within the semiconductor substrate within the opening. A second silicon nitride layer is deposited overlying the first silicon nitride layer and the oxide layer within the opening. The second silicon nitride layer is etched away to leave spacers on the sidewalls of the first silicon nitride layer. The oxide layer and the nitrogen implanted area of the semiconductor substrate within the opening are etched away where they are not covered by the spacers.

Abstract: A field oxide formation method involving a primary field oxidation, which is carried out at a predetermined low temperature to form a field oxide film having a thickness smaller than a target thickness, and a secondary field oxidation, which is carried out at a higher temperature capable of relatively reducing the occurrence of a field thinning phenomenon, to form the remaining thickness portion of the target field oxide film. The field thinning phenomenon involved in a field oxidation is reduced. The characteristics of a finally produced gate oxide film is also improved. Consequently, the throughput and reliability of semiconductor devices having gate oxide films are improved.

Abstract: An evaluating method of an HSG silicon film using atomic force microscopy (AFM). The characteristics of the HSG silicon film are measured and expressed with quantitative values using AFM. The above values are compared to values written in the working specification, to thereby evaluate the HSG silicon film and control the conditions of forming the HSG silicon film. Also, the capacitor where the HSG silicon film is interposed is formed, and then the capacitance of the capacitor is measured to determine the HSG height of the HSG silicon film for ensuring desired capacitance and conditions of forming the HSG silicon film. Accordingly, the characteristics of the HSG silicon film may be analyzed without damaging the semiconductor substrate and a preferred working specification for forming the HSG silicon film may be realized, to thereby increase the reproducibility of the HSG silicon film.

Abstract: The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers is formed on the side walls of the gate structure. Then, source/drain structure of the device is fabricated. Next, the side wall spacers is removed to expose a portion of the source and drain. Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain. A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide. Polysilicon side wall spacers are then formed. A further polysilicon layer is subsequently deposited over the gate. Then, the polysilicon layer is patterned to define the floating gate. A dielectric is formed at the top of the floating gate. A conductive layer is formed on the dielectric layer as control gate.

Abstract: Semiconductor devices having one or more asymmetric background dopant regions and methods of fabrication thereof are provided. The asymmetric background dopant regions may be formed using a patterned mask with wider openings than conventional masks while substantially maintaining device performance. This can, for example, facilitate the fabrication process and allow greater flexibility in the choice of photolithography tools.

Abstract: A container capacitor having a recessed conductive layer. The recessed conductive layer is typically made of polysilicon. The recessed structure reduces the chances of polysilicon "floaters," which are traces of polysilicon that remain on the surface of the substrate, coupling adjacent capacitors together to create short circuits. The disclosed method of creating such a recessed structure uses chemical mechanical planarization to remove the layer of polysilicon and an overlying layer of photoresist from the upper surface of the substrate in which a container is formed. A wet etch selectively isolates a rim of the polysilicon within the container to recess the a rim, while the remainder of the polysilicon in the container is protected by the layer of photoresist.

Abstract: The present method provides for the detection and assessment of the net charge in a PECVD oxide layer deposited on a surface of a semiconductor substrate. Electrical potential differences across PECVD oxide layers on as-produced semiconductor substrates are measured. Resultant PECVD oxide charge derivative values are plotted on an control chart and compared to calculated control parameters. All measurement techniques are non-contact and non-destructive, allowing them to be performed on as-processed semiconductor substrates at any time during or following a wafer fabrication process. In a first embodiment, a contact potential difference V.sub.CPD between a vibrating electrode and the semiconductor substrate is measured while the semiconductor substrate beneath the vibrating electrode is subjected to a constant beam of high intensity illumination. The resultant value of V.sub.CPD is equal to the electrical potential difference across the PECVD oxide layer V.sub.OX (plus a constant).

Abstract: A process for fabricating a transistor in which a first impurity distribution is introduced into a semiconductor substrate prior to the formation of a conductive gate structure on the semiconductor substrate. The substrate includes a channel region disposed between a source region and an LDD region. The LDD region is laterally disposed between a channel region and a drain region. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. A conductive gate structure is then formed on an upper surface of the gate dielectric layer. A first sidewall of the conductive gate is aligned over a boundary between the source region and the channel region. A second sidewall of the conductive gate is aligned above a boundary between the channel region and the LDD region. A second impurity distribution is then implanted into the semiconductor substrate.

Abstract: An isolation structure is provided by a method which includes forming a pad oxide layer on a semiconductor substrate and then forming a pad nitride layer on the pad oxide layer. An opening is then formed which extends through the pad nitride layer, the pad oxide layer, and into the semiconductor substrate. The pad nitride layer is then isotropically etched, thereby pulling-back the pad nitride layer from the portion of the opening extending through the pad oxide layer. An insulating layer is formed to fill in the opening including the portion of the opening formed by the pulling-back of the pad nitride layer. The deposited insulating layer is then planarized using the pulled-back nitride layer as a stopper layer. The pulled-back pad nitride layer and the pad oxide layer are then removed.

Abstract: A method for forming square shape images in a lithographic process is disclosed wherein a first plurality of lines running in a first direction is defined in a first, usually sacrificial, layer, and then a second resist is defined wherein the lines run in an intersecting pattern to those of the first layer, thereby creating cornered images wherever the first and second layer intersect and in the open areas between the lines. Methods are proposed for developing the square intersecting areas and the square angle areas defined by the openings. Additionally, a photomask is disclosed in which the length and width of the cornered images are independently patterned using the two-exposure process.

Abstract: The present invention relates to a method for forming an isolation trench structure in a semiconductor substrate without causing deleterious topographical depressions in the upper surface thereof which cause current and charge leakage to an adjacent active area. The inventive method forms a pad oxide upon a semiconductor substrate, and then forms a nitride layer on the pad oxide. The nitride layer is patterned with a mask and etched to expose a portion of the pad oxide layer and to protect an active area in the semiconductor substrate that remains covered with the nitride layer. A second dielectric layer is formed substantially conformably over the pad oxide layer and the remaining portions of the first dielectric layer. A spacer etch is then carried out to form a spacer from the second dielectric layer. The spacer is in contact with the remaining portion of the first dielectric layer. An isolation trench etch follows the spacer etch.

Abstract: An improved DRAM cell using a novel buried reservoir capacitor is achieved. The method forms an array of N.sup.+ doped regions in a substrate. P-wells are formed in an epitaxy layer on the substrate. A field oxide (FOX) is formed surrounding the device areas aligned over the N.sup.+ regions. Holes are etched in the epi layer to the N.sup.+ regions, and a selective wet etch removes the N.sup.+ doped regions to form cavities. A thin dielectric layer is deposited on the cavity walls, and an N.sup.+ polysilicon layer is deposited and polished back to form the buried reservoir capacitors. The N.sup.+ polysilicon in the holes forms the capacitor node contacts for the FETs in the device areas. The array of DRAM cells is completed by growing a gate oxide, depositing and patterning a first polycide layer to form FET gate electrodes on the device areas over the capacitors, thereby providing increased capacitance while reducing the cell area.

Abstract: A system and method for providing a memory in a semiconductor is disclosed. In one aspect, the method and system include providing a source implant in the semiconductor, providing a first anneal of the source implant in an oxidizing agent, and providing a drain implant in the semiconductor after the first anneal. In another aspect, the method and system include providing a source implant and a drain implant in the semiconductor, providing a mask, and providing an anneal of the source implant, the drain implant, and the mask in an oxidizing agent. The mask exposes the source implant while limiting exposure of at least a portion of the drain implant.

Abstract: A method for forming DRAM capacitor that utilizes the formation of an oxide layer and the subsequent etch-removal of a portion of the oxide layer located in the gap between a first masking layer and a second masking layer in order to form the minimum separation required between the lower electrodes of adjacent capacitors. Furthermore, when the etching operation is carried on into the conductive layer that lies below the oxide layer, the lower electrode of the capacitor is also patterned out. The manufacturing process in this invention does not use the conventional photolithographic technique, and therefore will not be limited by the resolution of the light source. Consequently, distance between two neighboring capacitors can be reduced, and a higher capacitance for the capacitors can be obtained.