Patents Examined by Daniel Hyun Suh
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Patent number: 11837614Abstract: A subpixel including at least one second-conductivity-type pinned photodiode layer that forms a p-n junction with a substrate semiconductor layer, at least one floating diffusion region, and at least one transfer gate stack structure. The at least one transfer gate stack structure may at least partially laterally surround the at least one second-conductivity-type pinned photodiode layer with a total azimuthal extension angle in a range from 240 degrees to 360 degrees around a geometrical center of the second-conductivity-type pinned photodiode layer. The at least one transfer gate stack structure may include multiple edges that overlie different segments of a periphery of the at least one second-conductivity-type pinned photodiode layer, and the floating diffusion region includes a portion located between the first edge and the second edge. In addition, multiple transfer gate stack structures and multiple floating diffusion regions may be present in the subpixel.Type: GrantFiled: February 23, 2021Date of Patent: December 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Feng-Chien Hsieh, Yun-Wei Cheng, Wei-Li Hu, Kuo-Cheng Lee, Hsin-Chi Chen
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Patent number: 11817461Abstract: A light-emitting panel, a method making same, and a display panel are disclosed in the present disclosure. The light-emitting panel includes a light-emitting board which includes a substrate; a first metal layer disposed on the substrate; a gate insulating layer covering the first metal layer; and a second metal layer on a side of the gate insulating layer away from the first metal layer. The second metal layer includes a connection portion located in the bonding area of the light-emitting board, and a conductive protection layer formed by chemical plating is disposed on a surface of the connection portion.Type: GrantFiled: November 11, 2020Date of Patent: November 14, 2023Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Maoxia Zhu, Hongyuan Xu, Xu Wang
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Patent number: 11785859Abstract: Proposed is a magnetoresistance device, including a first layered magnetic material layer in which a magnetization direction is controlled depending on the voltage, a second layered magnetic material layer in which a magnetization direction is fixed in a predetermined direction, and a layered insulator layer interposed between the first and second layered magnetic material layers.Type: GrantFiled: February 1, 2021Date of Patent: October 10, 2023Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Jun Woo Choi, Sang Yeop Lee, Hyejin Ryu, Chaun Jang
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Patent number: 11776843Abstract: A process for transferring blocks from a donor to a receiver substrate, comprises: arranging a mask facing a free surface of the donor substrate, the mask having one or more openings that expose the free surface of the donor substrate, the openings distributed according to a given pattern; forming, by ion implantation through the mask, an embrittlement plane in the donor substrate vertically in line with at least one region exposed through the mask, the embrittlement plane delimiting a respective surface region; forming a block that is raised relative to the free surface of the donor substrate localized vertically in line with each respective embrittlement plane, the block comprising the respective surface region; bonding the donor substrate to the receiver substrate via each block located at the bonding interface, after removing the mask; and detaching the donor substrate along the localized embrittlement planes to transfer blocks onto the receiver substrate.Type: GrantFiled: March 25, 2020Date of Patent: October 3, 2023Assignee: SoitecInventors: Didier Landru, Bruno Ghyselen
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Patent number: 11744070Abstract: A semiconductor memory device comprises: first conductive layers arranged in a first direction; a first semiconductor layer facing the first conductive layers; a second semiconductor layer facing the first conductive layers; second conductive layers arranged in the first direction; third conductive layers arranged in the first direction; a third semiconductor layer facing the second conductive layers and connected to the first semiconductor layer; a fourth semiconductor layer facing the third conductive layers and connected to the second semiconductor layer; a fourth conductive layer facing the third semiconductor layer; and a fifth conductive layer connected to the third conductive layers. A distance from a central axis of the third semiconductor layer to a central axis of the fourth semiconductor layer is larger than a distance from a central axis of the first semiconductor layer to a central axis of the second semiconductor layer.Type: GrantFiled: March 12, 2021Date of Patent: August 29, 2023Assignee: KIOXIA CORPORATIONInventors: Toshiya Murakami, Kenji Tashiro, Hidenori Miyagawa, Reiko Kitamura
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Patent number: 11735615Abstract: An imaging device including: a photoelectric converter; a protection member provided on a light incidence side of the photoelectric converter; a substrate opposed to the protection member with the photoelectric converter interposed therebetween and having a first surface on the photoelectric converter side and a second surface opposed to the first surface; a rewiring layer provided in a selective region of the second surface of the substrate; and a protective resin layer provided on the second surface of the substrate, the second surface of the substrate having an external terminal coupling region exposed from the protective resin layer, and a stress relaxation region exposed from the protective resin layer and disposed at a position different from the external terminal coupling region.Type: GrantFiled: May 14, 2019Date of Patent: August 22, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshiaki Masuda, Tokihisa Kaneguchi
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Patent number: 11730063Abstract: The magnetoresistive effect element includes a first ferromagnetic layer, a second ferromagnetic layer, and a nonmagnetic layer positioned between the first ferromagnetic layer and the second ferromagnetic layer, and at least one of the first ferromagnetic layer and the second ferromagnetic layer includes a Heusler alloy layer including a crystal region and an amorphous region.Type: GrantFiled: December 8, 2020Date of Patent: August 15, 2023Assignee: TDK CORPORATIONInventors: Kazuumi Inubushi, Katsuyuki Nakada, Shinto Ichikawa
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Patent number: 11729974Abstract: A semiconductor memory device includes a word line extending in a vertical direction on a substrate, a channel layer surrounding the word line to configure a cell transistor and having a horizontal ring shape with a predetermined horizontal width, a bit line disposed at one end of the channel layer in a first horizontal direction and extending in a second horizontal direction perpendicular to the first horizontal direction, and a cell capacitor disposed at other end of the channel layer in the first horizontal direction, the cell capacitor including an upper electrode layer extending in the vertical direction, a lower electrode layer surrounding the upper electrode layer, and a capacitor dielectric layer disposed between the upper electrode layer and the lower electrode layer.Type: GrantFiled: February 23, 2021Date of Patent: August 15, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyunghwan Lee, Yongseok Kim, Hyuncheol Kim, Hyeoungwon Seo, Sungwon Yoo, Jaeho Hong
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Patent number: 11637197Abstract: An epitaxial structure of a GaN-based radio frequency device based on a Si substrate and a manufacturing method thereof are provided. The epitaxial structure is composed of a Si substrate (1), an AlN nucleation layer (2), AlGaN buffer layers (3, 4, 5), a GaN:Fe/GaN high-resistance layer (6), a GaN superlattice layer (7), a GaN channel layer (8), an AlGaN barrier layer (9) and a GaN cap layer (10) which are stacked in turn from bottom to top, wherein the GaN:Fe/GaN high-resistance layer (6) is composed of an intentional Fe-doped GaN layer and an unintentional doped GaN layer which are alternately connected; the GaN superlattice layer (7) is composed of a low-pressure/low V/III ratio GaN layer and a high-pressure/high V/III ratio GaN layer which are periodically and alternately connected.Type: GrantFiled: September 16, 2019Date of Patent: April 25, 2023Assignees: ZHONGSHAN INSTITUTE OF MODERN INDUSTRIAL TECHNOLOGY, SOUTH CHINA UNIVERSITY OF TECHNOLOGY, SOUTH CHINA UNIVERSITY OF TECHNOLOGYInventors: Hong Wang, Quanbin Zhou