Abstract: Systems and computer program products are provided for optimizing selection of files for eviction from a first storage pool to free up a predetermined amount of space in the first storage pool. A method includes analyzing an effective space occupied by each file of a plurality of files in the first storage pool, identifying, from the plurality of files, one or more data blocks making up a file to free up the predetermined amount of space based on the analysis of the effective space of each file of the plurality of files, selecting one or more of the plurality of files as one or more candidate files for eviction, based on the identified one or more data blocks, and evicting the one or more candidate files for eviction from the first storage pool to a second storage pool.

Abstract: Systems and computer program products are provided for optimizing selection of files for deletion from one or more data storage devices to free up a predetermined amount of space in the one or more data storage devices. A method includes analyzing an effective space occupied by each file of a plurality of files in the one or more data storage devices, identifying, from the plurality of files, one or more data blocks making up a file to free up the predetermined amount of space based on the analysis of the effective space of each file of the plurality of files, selecting one or more of the plurality of files as one or more candidate files for deletion, based on the identified one or more data blocks, and deleting the one or more candidate files for deletion from the one or more data storage devices.

Abstract: Methods, systems, and computer program products are provided for optimizing selection of files for deletion from one or more data storage devices to free up a predetermined amount of space in the one or more data storage devices. A method includes analyzing an effective space occupied by each file of a plurality of files in the one or more data storage devices, identifying, from the plurality of files, one or more data blocks making up a file to free up the predetermined amount of space based on the analysis of the effective space of each file of the plurality of files, selecting one or more of the plurality of files as one or more candidate files for deletion, based on the identified one or more data blocks, and deleting the one or more candidate files for deletion from the one or more data storage devices.

Abstract: A data processing apparatus may include a plurality of buffer units that stores data, a data write control unit that writes input data to any one of the plurality of buffer units by exclusively controlling the plurality of buffer units, and a data read control unit that reads data to be output from any one of the plurality of buffer units by exclusively controlling the plurality of buffer units. The data write control unit may output a data write completion signal indicating that the writing of the data is completed when the writing of the input data is completed. The data read control unit may output a data read completion signal indicating that the reading of the data is completed when the reading of the data to be output is completed.

Abstract: Methods, systems, and computer program products are provided for optimizing selection of files for eviction from a first storage pool to free up a predetermined amount of space in the first storage pool. A method includes analyzing an effective space occupied by each file of a plurality of files in the first storage pool, identifying, from the plurality of files, one or more data blocks making up a file to free up the predetermined amount of space based on the analysis of the effective space of each file of the plurality of files, selecting one or more of the plurality of files as one or more candidate files for eviction, based on the identified one or more data blocks, and evicting the one or more candidate files for eviction from the first storage pool to a second storage pool.

Abstract: A device requiring address allocation, a device system, and an address allocation method. A control device in the device system transmits currently allocated address information and a contention start signal to each device requiring address allocation in the device system through a bus, and the devices requiring address allocation with address allocation flag information being that no address information is allocated output an address contention signal. When outputting the address contention signal, each device requiring address allocation determines whether the currently allocated address information is available according to whether the other devices requiring address allocation with address allocation flag information being that no address information is allocated already output address contention signals.

Abstract: A system and method of detecting cache inconsistencies among distributed data centers is described. Key-based sampling captures a complete history of a key for comparing cache values across data centers. In one phase of a cache inconsistency detection algorithm, a log of operations performed on a sampled key is compared in reverse chronological order for inconsistent cache values. In another phase, a log of operations performed on a candidate key having inconsistent cache values as identified in the previous phase is evaluated in near real time in forward chronological order for inconsistent cache values. In a confirmation phase, a real time comparison of actual cache values stored in the data centers is performed on the candidate keys identified by both the previous phases as having inconsistent cache values. An alert is issued that identifies the data centers in which the inconsistent cache values were reported.

Abstract: A flash memory device includes a flash memory unit; and a control unit configured to perform control so that data having a size smaller than a block size of the flash memory unit is sequentially written to the flash memory unit.

Abstract: According an embodiment, a semiconductor memory device includes a semiconductor memory chip to store plural pieces of data that are written and read in units of a page and are erased in units of a block including plural pages; a discarding unit to discard, after the data is written in the semiconductor memory chip with a logic address being designated, at least a portion of valid data among the plural pieces of data; a compaction unit to write the valid data excluding the discarded data in a second block among the valid data stored in a first block and erase the first block; and a controller to output, in response to a request for reading the discarded data, a response indicating that the data is unable to be read. When all the valid data included in a block are discarded, the discarding unit erases the block.

Abstract: A memory management method including the steps of storing a value and writing data. The storing a value step stores a value representative of a number of erase/write cycles that a subset of memory space of a first memory has undergone. The first memory having an assigned predetermined maximum number of erase/write cycles. The writing data step writes data to the subset of memory space dependent upon whether the value is below the predetermined maximum number.

Abstract: A memory system includes a nonvolatile memory device, a memory controller for controlling the nonvolatile memory device and a virtual data interface layer that manages reading and/or writing of patterned data from/to the nonvolatile memory device. In a read operation, the virtual data interface layer generates patterned data that is requested to be read. Accordingly, a read speed of the memory system may be improved.

Abstract: A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic is coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array. A gate is coupled to the output of the random-access memory array and is configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.

Abstract: Optimizing cache-resident area where cache residence control in units of LUs is employed to a storage apparatus that virtualizes the capacity by acquiring only a cache area of a size that is the same as the physical capacity assigned to the LU. An LU is a logical space resident in cache memory is configured by a set of pages acquired by dividing a pool volume as a physical space created by using a plurality of storage devices in a predetermined size. When the LU to be resident in the cache memory is created, a capacity corresponding to the size of the LU is not initially acquired in the cache memory, a cache capacity that is the same as the physical capacity allocated to a new page is acquired in the cache memory each time when the page is newly allocated, and the new page is resident in the cache memory.

Abstract: A method and apparatus for auto-tuning memory is provided. Memory on a computer system comprises at least one shared memory area and at least one private memory area. Addresses in the shared memory area are accessible to multiple processes. Addresses in the private memory area are dedicated to individual processes. Initially, a division in the amount of memory is established between the shared and private memory areas. Subsequently, a new division is determined. Consequently, memory from one memory area is “given” to the other memory area. In one approach, such sharing is achieved by causing the shared and private memory areas to be physically separate from each other both before and after a change in the division. The division of the amount of memory may be changed to a new division by deallocating memory from one of the memory areas and allocating that memory to the other of the memory areas.

Abstract: The present invention provides a storage system for migrating a storage apparatus. The storage system comprises the steps of: defining a logical volume on a storage apparatus to be migrated coupled to a first controller as a local volume coupled to a second controller; setting to receive an access targeted to the logical volume through an input/output port of the storage apparatus to be migrated, as the local volume coupled to the second controller; blocking the input/output port of the storage apparatus to be migrated; connecting the other input/output port of the storage apparatus to the second control apparatus.

Abstract: In a virtual disk library device access of data stored in a tape can be conducted at a high speed with a high-speed archiving process from a disk to the tape in units of LUs maintained. The efficiency of update of the data stored in the tape can be improved. In this system, when the data stored in the tape is to be accessed with a high-speed archiving process in units of LUs from the disk to the tape maintained, a disk staging process is performed in the unit of a page that is smaller than the unit of an LU, and accordingly, high-speed access can be implemented. In addition, when an update process for the data (LU) stored in the tape is performed, the host can be responded by only staging an update target page of the LU, and a prior disk staging process is performed for the remaining pages of the LU in the background. Accordingly, when the data is re-stored in the tape, immediately storing the data in the tape can be performed without performing a staging process.

Abstract: Optimizing cache-resident area where cache residence control in units of LUs is employed to a storage apparatus that virtualizes the capacity by acquiring only a cache area of a size that is the same as the physical capacity assigned to the LU. An LU is a logical space resident in cache memory is configured by a set of pages acquired by dividing a pool volume as a physical space created by using a plurality of storage devices in a predetermined size. When the LU to be resident in the cache memory is created, a capacity corresponding to the size of the LU is not initially acquired in the cache memory, a cache capacity that is the same as the physical capacity allocated to a new page is acquired in the cache memory each time when the page is newly allocated, and the new page is resident in the cache memory.

Abstract: In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data.

Abstract: In one embodiment, a processor regularly writes one or more cache entries back to memory to reduce the likelihood of cache soft errors. The regularly occurring write backs operate independently of Least Recently Used (LRU) status of the entries so that all entries are flushed.

Abstract: The multiprocessor system includes multiple cells having identical functions, and each of the multiple cells has a processor, a cache memory, and a main memory. The multiple cells include the first cell as a request cell, the second cell as a home cell, and the third cell as an owner cell. The latest version of the target data stored in the main memory of the second cell is stored in the cache memory of the third cell. When the first cell issues a read request for the target data to the second cell, the second cell issues a snoop request to the third cell in response to the read request. The third cell directly transmits the target data to the first cell in response to the snoop request. Also, the third cell issues the reply write back to the second cell in response to the snoop request. The first cell issues a request write back to the same address as that of the target data in the second cell.