Abstract: This semiconductor device comprises a substrate, a first wiring part, a second wiring part, and a semiconductor element. The first wiring part includes a first through-electrode, first main-surface wiring, and a first wiring electrode. The second wiring section includes a second through-electrode, second main-surface wiring, and a second wiring electrode. An upper surface is depressed toward the interior of the first through-electrode. The first wiring electrode is joined to a first element electrode of the semiconductor element by a first joining member. The second wiring electrode is joined to a second element electrode of the semiconductor element by a second joining member. The first wiring electrode, which is formed on an upper surface of the first main-surface wiring, is larger than the second wiring electrode, which is formed on an upper surface of the second main-surface wiring, as seen from the thickness direction.

Abstract: A semiconductor device having a semiconductor substrate with first and second main surfaces that face one another in a thickness direction, and a circuit layer disposed on the first main surface. The circuit layer has a first electrode layer on the semiconductor substrate, a dielectric layer on the first electrode layer, a second electrode layer on the dielectric layer, and first and second outer electrodes electrically connected to the first and second electrode layers, respectively. The semiconductor substrate has a first end-portion region in which the circuit layer is not provided on the semiconductor substrate and on the side of the first end surface. In the first end-portion region, a first exposed portion is provided that is exposed between the first main surface and the first end surface.

Abstract: A method for manufacturing a stacked thin film of an embodiment includes forming a p-electrode on a substrate, forming a film that mainly contains a cuprous oxide and/or a complex oxide of cuprous oxides on the p-electrode, and performing an oxidation treatment on the film that mainly contains the cuprous oxide and/or the complex oxide of cuprous oxides. An ozone partial pressure in the oxidation treatment is 5 [Pa] or more and 200 [Pa] or less, a treatment temperature in the oxidation treatment is 273 [K] or more and 323 [K] or less, and a treatment time in the oxidation treatment is 1 second or more and 60 minutes or less.

Abstract: A semiconductor chip includes a lower wiring layer, a multilayer wiring layer formed on the lower wiring layer, and an upper wiring layer formed on the multilayer wiring layer. Here, a thickness of a wiring provided in the lower wiring layer is larger than a thickness of each of a plurality of wirings provided in the multilayer wiring layer, and a thickness of a wiring provided in the upper wiring layer is larger than the thickness of each of the plurality of wirings provided in the multilayer wiring layer. A lower inductor which is a component of a transformer is provided in the lower wiring layer, and an upper inductor which is a component of the transformer is provided in the upper wiring layer.

Abstract: A semiconductor package includes a connection structure having first and second surfaces opposing each other and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and including connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; and a second redistribution layer disposed on the encapsulant; a wiring structure connecting the first and second redistribution layers to each other and extending in a stacking direction; and a heat dissipation element disposed on at least a portion of the second surface of the connection structure.

Abstract: The present invention provides a QFN packaging structure and QFN packaging method. By providing the insulating layer on the outer side of the leads of the QFN packaging structure, a short circuit between the leads and the electromagnetic shielding layer can be prevented. In addition, the grounding lead is exposed from the insulating layer, such that the electromagnetic shielding layer is grounded via the grounding lead, thereby realizing the electromagnetic shielding design of the QFN packaging structure.

Abstract: A method for manufacturing a semiconductor device, the method including forming a fin type pattern including a lower pattern and an upper pattern on a substrate, the upper pattern including a plurality of sacrificial layers and a plurality of sheet patterns alternately stacked on the lower pattern; forming a field insulating film on the substrate and the fin type pattern such that the field insulation film covers side walls of the lower pattern; forming a passivation film on the field insulating film such that the passivation film extends along an upper surface of the field insulating film; and removing the plurality of sacrificial layers after forming the passivation film.

Abstract: A semiconductor device includes a semiconductor chip having first and second main electrodes disposed on opposite surfaces of a silicon carbide substrate, first and second heat dissipation members disposed so as to sandwich the semiconductor chip, and joining members disposed between the first main electrode and the first heat dissipation member and between the second main electrode and the second heat dissipation member. At least one of the joining members is made of a lead-free solder having an alloy composition that contains 3.2 to 3.8 mass % Ag, 0.6 to 0.8 mass % Cu, 0.01 to 0.2 mass % Ni, x mass % Sb, y mass % Bi, 0.001 to 0.3 mass % Co, 0.001 to 0.2 mass % P, and a balance of Sn, where x and y satisfy relational expressions of x+2y?11 mass %, x+14y?42 mass %, and x?5.1 mass %.

Abstract: A method of manufacturing a display device includes providing a mother substrate including a first cell region, a second cell region, and a peripheral region. First alignment keys arranged in a first direction in the peripheral region on the mother substrate is formed such that the first alignment keys are adjacent to a first side portion of each of first and second light emitting structures, while forming the first and second light emitting structures in the first and second cell regions on the mother substrate, respectively. A photoresist is formed in a second direction on the first and second light emitting structures by using a coater such that the photoresist does not to overlap the first alignment keys. The mother substrate is rotated at a preset angle. A light is irradiated to the photoresist by moving an exposer in a direction in which the first alignment keys are arranged.

Abstract: A semiconductor device has a substrate and a slot formed in the substrate. A first electrical component is disposed over the substrate adjacent to the slot. An encapsulant is deposited over the first electrical component with a surface of the encapsulant coplanar to a surface of the substrate within the slot. A shielding layer is formed over the encapsulant and physically contacting the surface of the substrate within the slot. The substrate is singulated to form a semiconductor package with the first electrical component after forming the shielding layer.

Abstract: A method of manufacturing a silicon carbide semiconductor power device is provided. In the method, the power device in high voltage (HV) region and CMOS device in the low voltage (LV) region are formed together, so the cost and time can be saved efficiently. First, a first drift layer is formed on a substrate, and then a shielding region is formed in the first drift layer. The shielding region includes a continuous region in the LV region. Then, a second drift layer is formed on the first drift layer. A pick-up region is formed in the second drift layer, wherein the pick-up region connects to the continuous region of the shielding region, and then NMOS and PMOS in the LV region and the power device in HV region are formed simultaneously. NMOS and PMOS are surrounded by the pick-up region and the continuous region, thereby minimizing body effect.