Abstract: A semiconductor device includes a substrate including a circuit region and a protection region surrounding the circuit region, a plurality of insulating layers sequentially provided on the substrate, a moisture blocking structure extending in the plurality of insulating layers in the protection region of the substrate and surrounding the circuit region, the moisture blocking structure including a first plurality of wiring layers vertically provided on a surface of the substrate, where an uppermost wiring layer of the first plurality of wiring layers comprises a first via, and a metal wiring provided on the first via, and a crack stopper extending in the plurality of insulating layers in the protection region of the substrate and surrounding the moisture blocking structure, the crack stopper including a second plurality of wiring layers vertically provided on the surface of the substrate.

Abstract: A structure includes an integrated circuit (IC) chip including a substrate. At least two input/output (I/O) openings extend inwardly from an exterior surface of the IC chip. The I/O openings can be used to connect any sort of I/O device, such as an external optical device like a laser. Each I/O opening is separated from an adjacent I/O opening by a wall. An opening extends through the wall to each of the at least two I/O openings, and a moisture barrier is on inner surfaces of each I/O opening and the opening. The opening may reduce stress and may reduce sharp corners in the I/O openings to reduce damage to the moisture barrier.

Abstract: Power module packaged in a housing accommodating a carrying substrate forming a plurality of connection regions of conductive material. An electronic component is arranged inside the housing, attached to a connection region of the plurality of connection regions. An electrical connector, coupled to the electronic component, extends towards the main surface of the housing and is accessible from the outside of the housing. The electrical connector has a tubular portion forming a pillar fixed to a pin which protrudes from the greater surface of the housing. The housing includes a packaging mass of electrically insulating material that embeds the pillar and blocks it therein.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure also includes a gate structure including a first portion wrapping around the first nanostructures and a second portion wrapping around the second nanostructures. The semiconductor structure also includes a dielectric feature sandwiched between the first portion and the second portion of the gate structure. In addition, the dielectric feature includes a bottom portion and a top portion over the bottom portion, and the top portion of the dielectric feature includes a shell layer and a core portion surrounded by the shell layer.

Abstract: An arrangement for cooling semiconductor components includes a cooling body base with a component side and a structural element side opposite the component side, wherein the semiconductor components are arrangeable in succession in the flow direction of a cooling medium, the structural element side are configured to increase its surface area by structural elements, and the structural element side is configured such that a density of structural elements involved in the cooling increases in the flow direction with regard to cooling zones.

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a device layer including a plurality of transistor structures. A front-end routing layer is above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors. A backside metal structure is below the device layer. A conductive feedthrough structure is directly coupling the backside metal structure to the front-end routing layer.

Abstract: A semiconductor device, including a case that has a first power terminal including a first bonding area and a second power terminal including a second bonding area, and an insulating unit located between the first power terminal and the second power terminal, and having a shape of a flat plate, the insulating unit being bonded to the case. The insulating unit has a first insulating portion in a sheet form, and a second insulating portion which covers an upper surface, a lower surface, or both the upper and lower surfaces, of the first insulating portion. The first bonding area and the second bonding area are exposed from the insulating unit and from the case.

Abstract: A power module including at least one power device, an insulation thermally conductive layer, and a heat dissipation device is provided. The insulation thermally conductive layer has a patterned circuit layer. The power device is disposed on the patterned circuit layer and is electrically connected to the patterned circuit layer. The heat dissipation device includes a heat dissipation plate and a heat dissipation base. The heat dissipation plate has a first surface and a second surface opposite to each other, and the insulation thermally conductive layer is disposed on the first surface. The heat dissipation base is partially bonded to the heat dissipation plate, and a chamber is formed between the heat dissipation plate and the heat dissipation bases. The heat dissipation base has a plurality of first heat dissipation bumps located in the chamber.

Abstract: The systems and cold plate pedestal and assembly described decrease mechanical stresses in integrated circuits, while also providing efficient thermal coupling between heat producing components and a cold plate. A cold plate assembly includes a cold plate with a pedestal portion a groove formed in a surface of the pedestal portion. The cold plate assembly also includes a thermal pad layer formed in the groove and a phase change material (PCM) layer formed on the surface of the pedestal portion and a surface of the thermal pad layer formed in the groove.

Abstract: A composite component includes an interposer structure and an electronic component. The interposer structure has a Si base layer having a first main surface and a second main surface opposite to each other, a redistribution layer formed on the first main surface, through-Si vias electrically connected to the redistribution layer and penetrating the Si base layer, an interposer electrode facing the second main surface, an adhesive layer and an insulating layer. The electronic component has component electrodes respectively connected to the through-Si vias. The electronic component is provided between the interposer electrode and the Si base layer. The insulating layer is disposed between the component electrodes of the electronic component. In the electronic component, the component electrode and a surface on which the insulating layer is disposed are bonded to the second main surface of the Si base layer with the adhesive layer interposed therebetween.

Abstract: Provided are a display panel and a display device. The display panel includes a display region and a non-display region. The display region includes multiple first power signal lines, and the multiple first power signal lines extend along a first direction. The non-display region includes a power bus and a power lead-out wire. The power bus includes a first bus section and a second bus section, and along the first direction, the first bus section is connected to the power lead-out wire. The display region includes a first display region and a second display region, along the first direction, an overlapping region exists between a projection of the first display region on the power bus and the first bus section, an overlapping region exists between a projection of the second display region on the power bus and the second bus section.

Abstract: This semiconductor device comprises a substrate, a first wiring part, a second wiring part, and a semiconductor element. The first wiring part includes a first through-electrode, first main-surface wiring, and a first wiring electrode. The second wiring section includes a second through-electrode, second main-surface wiring, and a second wiring electrode. An upper surface is depressed toward the interior of the first through-electrode. The first wiring electrode is joined to a first element electrode of the semiconductor element by a first joining member. The second wiring electrode is joined to a second element electrode of the semiconductor element by a second joining member. The first wiring electrode, which is formed on an upper surface of the first main-surface wiring, is larger than the second wiring electrode, which is formed on an upper surface of the second main-surface wiring, as seen from the thickness direction.

Abstract: A semiconductor device having a semiconductor substrate with first and second main surfaces that face one another in a thickness direction, and a circuit layer disposed on the first main surface. The circuit layer has a first electrode layer on the semiconductor substrate, a dielectric layer on the first electrode layer, a second electrode layer on the dielectric layer, and first and second outer electrodes electrically connected to the first and second electrode layers, respectively. The semiconductor substrate has a first end-portion region in which the circuit layer is not provided on the semiconductor substrate and on the side of the first end surface. In the first end-portion region, a first exposed portion is provided that is exposed between the first main surface and the first end surface.

Abstract: A method for manufacturing a stacked thin film of an embodiment includes forming a p-electrode on a substrate, forming a film that mainly contains a cuprous oxide and/or a complex oxide of cuprous oxides on the p-electrode, and performing an oxidation treatment on the film that mainly contains the cuprous oxide and/or the complex oxide of cuprous oxides. An ozone partial pressure in the oxidation treatment is 5 [Pa] or more and 200 [Pa] or less, a treatment temperature in the oxidation treatment is 273 [K] or more and 323 [K] or less, and a treatment time in the oxidation treatment is 1 second or more and 60 minutes or less.

Abstract: A semiconductor chip includes a lower wiring layer, a multilayer wiring layer formed on the lower wiring layer, and an upper wiring layer formed on the multilayer wiring layer. Here, a thickness of a wiring provided in the lower wiring layer is larger than a thickness of each of a plurality of wirings provided in the multilayer wiring layer, and a thickness of a wiring provided in the upper wiring layer is larger than the thickness of each of the plurality of wirings provided in the multilayer wiring layer. A lower inductor which is a component of a transformer is provided in the lower wiring layer, and an upper inductor which is a component of the transformer is provided in the upper wiring layer.

Abstract: A semiconductor package includes a connection structure having first and second surfaces opposing each other and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and including connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; and a second redistribution layer disposed on the encapsulant; a wiring structure connecting the first and second redistribution layers to each other and extending in a stacking direction; and a heat dissipation element disposed on at least a portion of the second surface of the connection structure.

Abstract: The present invention provides a QFN packaging structure and QFN packaging method. By providing the insulating layer on the outer side of the leads of the QFN packaging structure, a short circuit between the leads and the electromagnetic shielding layer can be prevented. In addition, the grounding lead is exposed from the insulating layer, such that the electromagnetic shielding layer is grounded via the grounding lead, thereby realizing the electromagnetic shielding design of the QFN packaging structure.

Abstract: A method for manufacturing a semiconductor device, the method including forming a fin type pattern including a lower pattern and an upper pattern on a substrate, the upper pattern including a plurality of sacrificial layers and a plurality of sheet patterns alternately stacked on the lower pattern; forming a field insulating film on the substrate and the fin type pattern such that the field insulation film covers side walls of the lower pattern; forming a passivation film on the field insulating film such that the passivation film extends along an upper surface of the field insulating film; and removing the plurality of sacrificial layers after forming the passivation film.

Abstract: A semiconductor device includes a semiconductor chip having first and second main electrodes disposed on opposite surfaces of a silicon carbide substrate, first and second heat dissipation members disposed so as to sandwich the semiconductor chip, and joining members disposed between the first main electrode and the first heat dissipation member and between the second main electrode and the second heat dissipation member. At least one of the joining members is made of a lead-free solder having an alloy composition that contains 3.2 to 3.8 mass % Ag, 0.6 to 0.8 mass % Cu, 0.01 to 0.2 mass % Ni, x mass % Sb, y mass % Bi, 0.001 to 0.3 mass % Co, 0.001 to 0.2 mass % P, and a balance of Sn, where x and y satisfy relational expressions of x+2y?11 mass %, x+14y?42 mass %, and x?5.1 mass %.

Abstract: A method of manufacturing a display device includes providing a mother substrate including a first cell region, a second cell region, and a peripheral region. First alignment keys arranged in a first direction in the peripheral region on the mother substrate is formed such that the first alignment keys are adjacent to a first side portion of each of first and second light emitting structures, while forming the first and second light emitting structures in the first and second cell regions on the mother substrate, respectively. A photoresist is formed in a second direction on the first and second light emitting structures by using a coater such that the photoresist does not to overlap the first alignment keys. The mother substrate is rotated at a preset angle. A light is irradiated to the photoresist by moving an exposer in a direction in which the first alignment keys are arranged.