Abstract: The present disclosure provides a storage device, including: at least one first storage region, at least one drive module, and at least one amplification module. The drive module is arranged on both sides of each of the first storage regions in a word line direction, and the amplification module is arranged on both sides of each of the first storage regions in a bit line direction. Each of the first storage regions includes at least one hybrid storage block arranged side by side in the word line direction and configured to store data and an on die error correcting code (OD-ECC).

Abstract: A memory device includes a plurality of multi-bit cells, wherein each of the plurality of multi-bit cells includes a plurality of bit cells commonly connected to a column selection line, respectively connected to a plurality of write word lines, and respectively connected to a plurality of read word lines and an input circuit configured to provide a first signal corresponding to a bit to be written, to the plurality of bit cells, wherein each of the plurality of bit cells includes a latch circuit configured to receive the first signal in response to a write word line being activated and latch the first signal in response to the write word line being deactivated or a column selection line being deactivated, and a read circuit configured to output the first signal stored in the latch circuit to a bit line in response to a read word line being activated.

Abstract: Various implementations described herein are related to a device with a first clock generator that provides a first pulse signal based on a clock signal, wherein the first clock generator has a first tracking circuit that provides a first reset signal based on the first pulse signal. The device may include a second clock generator that provides a second pulse signal based on the clock signal, wherein the second clock generator has a second tracking circuit that provides a first control signal based on the second pulse signal. Also, the device may include a third clock generator that provides a third pulse signal based on the first reset signal, wherein the third clock generator has a logic circuit that provides a second control signal based on the third pulse signal.

Abstract: A memory core circuit includes: (i) a memory cell array having sub cell arrays therein, and (ii) a core control circuit having sub peripheral circuits therein, such that each sub peripheral circuit extends underneath a corresponding sub cell array. Each sub cell array includes memory cells respectively connected to wordlines and bitlines. Each sub peripheral circuit includes sub wordline drivers configured to drive the wordlines, bitline sense amplifiers configured to sense voltages of the bitlines, a row decoding circuit configured to control the sub wordline drivers to select one of the wordlines, a power circuit configured to supply power to each sub peripheral circuit, and a control circuit configured to control operation of each sub peripheral circuit. By using a CoP structure that efficiently provides the core control circuit, the size of the memory core circuit may be reduced and a design margin may be enhanced.

Abstract: Embodiments of the disclosed technology relate to the operation of memory devices, and more particularly to sub-block mode (SBM) pre-charge operation sequences. One example embodiment provides a novel logic design of the control circuitry of a memory device using comments/instructions for the control circuitry. By virtue of the features of the disclosed technology, the control circuitry can effect pre-charging of an inner or middle vertical sub-block of a NAND string in a memory array. In some examples the NAND string has at least three vertical sub-blocks of non-volatile memory cells.

Abstract: The present technology relates to an electronic device. According to the present technology, a memory device may include a plurality of memory cells, a read and write circuit, and a program controller. The plurality of memory cells may be connected to a plurality of channels passing through a plurality of word lines. The program controller may control the read and write circuit to perform a sensing operation on first memory cells and second memory cells among the plurality of memory cells during differently set sensing time periods. The first memory cells may be connected to first channels adjacent to a plurality of slits, among a plurality of channels separated by the plurality of slits. The second memory cells may be connected to second channels farther from the plurality of slits than the first channels.

Abstract: A semiconductor device includes a first memory array, a first bit line, a second memory array, a second bit line, a first conductive line and a first control circuit. The first bit line crosses over and is coupled to the first memory array, and extends along a first direction. The second bit line crosses over the second memory array, and is coupled to the first bit line. The first conductive line crosses over the second memory array and a part of the first memory array, and is configured to operate as a part of a first capacitor. The first control circuit is configured to couple the first conductive line to the second bit line when the first memory array is written.

Abstract: Provided herein may be a memory device for performing a program operation including program loops and a method of operating the same. The method of operating a memory device may include performing a first program loop of increasing threshold voltages of first memory cells selected by a first drain select line among a plurality of memory cells coupled to a word line, performing a second program loop of increasing threshold voltages of second memory cells selected by a second drain select line among the plurality of memory cells, and alternately repeating the first program loop and the second program loop such that respective threshold voltages of the first memory cells and the second memory cells are increased to respective threshold voltages corresponding to respective target program states.

Abstract: In an example, a system includes an SRAM configured to store a plurality of access control rules, where each rule is stored in a separate row. The SRAM is configured to store a plurality of context entries, where each context entry is stored in a separate row. The system includes a controller configured to receive a request for an access control rule for a memory location from a first context. The controller is configured to search one or more access control rules for the first context, where access control rules for the first context are stored in a binary tree format. The controller is configured to, responsive to finding the access control rule for the memory location, return the access control rule to the first context. The controller is configured to, responsive to not finding the access control rule, return a null notification to the first context.

Abstract: A memory controller coupled to a memory device including an array of memory cells, each memory cell being set to one of 2N states corresponding to a piece of N-bits data, where N is an integer greater than 1, and the array of memory cells being partitioned into one or more units. The memory controller is coupled to the memory device and configured to, upon executing instructions, obtain, from the memory device, a number P of memory cells in a unit of the units that are in one or more programmed states of the 2N states; calculate, based on the number P, a compensated read voltage with an offset from a default read voltage; and provide, to the memory device, the compensated read voltage for a read operation performed on a selected memory cell of the memory cells in a unit of the units.

Abstract: An ultra-low-voltage static random access memory (SRAM) cell for eliminating half-select-disturbance under a bit interleaving structure includes a cross-coupled inverter pair, two N-type write transistors NM1 and NM2, two P-type write transistors PM1 and PM2, and two N-type transistors NM3 and NM4, where the two N-type transistors NM3 and NM4 form a readout path. The present disclosure can be applied to applications with a storage requirement at an ultra-low voltage, especially applications with certain requirements for an access speed and reliability of an SRAM at a low voltage. Compared with other different SRAM cells, the ultra-low-voltage SRAM cell can achieve higher read and write working frequencies with similar energy consumptions.

Abstract: A method for reading data from a non-volatile memory array having memory cells configured to store one bit information, including powering on the array, where information from at least first and second memory cells is collectively associated with one bit of sensible data; reading first and second memory cell values by comparing a reference value to an electrical property value of the respective memory cell; adjusting the reference value when at least the first and second memory cell values have a first combination of logic state values; reading the first and second memory cell values using the adjusted reference value to obtain a second combination of logic state values; and determining a sensible data bit value based on the second combination. The adjusted reference value lies in the space between first and second distributions of possible electrical property values respectively for the first and second memory cell values.

Abstract: Technology is disclosed herein for a dynamic bitscan. The dynamic bitscan may include performing a first bitscan of a first strict subset of memory cells. Then, based on results of the first bitscan, a determination is made whether to perform a second bitscan of a second strict subset of memory cells. Prior to the bitscan(s) a verify reference voltage may be applied to both strict subsets of memory cells. Skipping the second bitscan saves considerable time. However, the second bitscan is performed at least sometimes, which increases accuracy. The first strict subset of memory cells and the second strict subset of memory cells may have different locations relative to some point in the block that contains the memory cells. The first strict subset of memory cells and the second strict subset may have different programming speeds.

Abstract: An impedance control strategy for a Data Mask Pin (DM pin) in a preset test mode is provided, so that the impedance of the DM pin in the preset test mode may be defined. In addition, the relation between a control signal configured to control whether to enable the DM pin in a Double Data Rate 5 SDRAM (DDR5) and a control signal configured to control whether the DM pin is a test object in a Package Output Driver Test Mode (PODTM) is specified. The impedance of the DM pin may be tested in the preset test mode.

Abstract: The present disclosure provides a memory bank and a memory. The memory bank includes: multiple memory arrays arranged along a first direction, each of the memory arrays being divided into at least two array units along a second direction, and the first direction and the second direction being perpendicular to each other; multiple read-write control circuits, the read-write control circuits being provided between adjacent two of the memory arrays; and multiple data signal lines configured to electrically connect the read-write control circuits and the array units; wherein, different array units of each of the memory arrays are electrically connected to different read-write control circuits through different data signal lines.

Abstract: An in-memory computing memory device includes: a plurality of computing memory cells forming a plurality of memory strings, the computing memory cells storing a plurality of weight values; a loading capacitor; and a measurement circuit. In IMC operations, a plurality of input voltages, corresponding to a plurality of input values, are input into the computing memory cells; a plurality of effective resistances of the computing memory cells are corresponding to the input voltages and the weight values; when a read voltage is applied to the plurality of computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents for charging the loading capacitor; and based a capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.

Abstract: A semiconductor device includes a control circuit configured to generate a buffer enable signal that is enabled when patterns of a strobe signal and an inverted strobe signal are preset patterns after the start of a write operation and configured to generate an internal strobe signal by dividing frequencies of an input strobe signal and an inverted input strobe signal, and a buffer circuit configured to generate the input strobe signal and the inverted input strobe signal from the strobe signal and the inverted strobe signal that are received when the buffer enable signal is enabled and configured to generate transfer data by receiving data for performing the write operation when the buffer enable signal is enabled.

Abstract: Provided is a memory device with a vertical channel structure. The memory device includes a memory cell array including a plurality of memory cells and a plurality of string selection lines, a negative charge pump configured to generate a bias voltage of a negative level, to be applied to at least one of the plurality of string selection lines, and a control logic circuit configured to apply, for a first period, a prepulse voltage to at least one unselected string selection line among the plurality of string selection lines excluding a selected string selection line to which a memory cell selected from among the plurality of memory cells is connected and thereafter apply the bias voltage to the at least one unselected string selection line so as to perform a read operation on the selected memory cell.

Abstract: Control logic in a memory device determines to initiate a string read operation on a first memory string of a plurality of memory strings in a block of a memory array, the block comprising a plurality of wordlines, wherein the first memory string is designated as a sacrificial string. The control logic further causes a read voltage to be applied to each of the plurality of wordlines concurrently and senses a level of current flowing through the sacrificial string while the read voltage is applied. In addition, the control logic identifies, based on the level of current flowing through the sacrificial string, whether a threshold level of read disturb has occurred on the block.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit configured to perform a verify operation that identifies threshold voltages of the plurality of memory cells by using a first verify voltage and a second verify voltage, and a program operation controller configured to control the peripheral circuit, after the verify operation is terminated and during a period in which a program voltage is applied to the plurality of memory cells, to apply a first control signal to a page buffer that is coupled to a first memory cell having a threshold voltage that is higher than the first verify voltage and lower than the second verify voltage, and apply a second control signal having a lower level voltage than the first control signal to the page buffer.