Abstract: A semiconductor device includes a memory cell array and a peripheral circuit. The memory cell array is coupled to a plurality of word lines and a plurality of bit lines. The peripheral circuit performs a deep-erase verification operation to determine whether a target memory cell has a threshold voltage that is lower than a first negative reference voltage by applying a second negative reference voltage that is lower than the first negative reference voltage to the target memory cell.

Abstract: Technology for in-memory computing. NAND memory cells are organized into calculation cell units based on one or more physical and/or operational characteristics of the NAND memory cells. Variances in physical and/or operational characteristics of the NAND memory cells in a calculation cell unit can negatively impact accuracy of the in-memory compute. NAND memory cell transistors that are similar to each other in the one or more physical and/or operational characteristics are placed into a calculation cell unit even if those memory cells are not adjacent to each other. Two memory cell transistors of one calculation cell unit may be separated by at least one memory cell transistor of a different calculation cell unit. Organizing NAND memory cell transistors into calculation cell units based on one or more physical and/or operational characteristics improves accuracy of NAND in-memory compute.

Abstract: Control logic in a memory device initiates a program operation including a first phase including applying a ramping voltage level to a set of wordlines of a memory device to boost a set of pillar voltages and a second phase including applying a set of programming pulses to a wordline associated with one or more memory cells of the memory device to be programmed to a set of programming levels, wherein each programming level of the set of programming levels is programmed by each programming pulse. During the first phase of the program operation, a first voltage applied to a drain-side select line (SGD) is adjusted from a first SGD voltage level to a second SGD voltage level.

Abstract: A non-volatile memory device includes a plurality of cell strings in a vertical direction, each of the plurality of cell strings including a plurality of memory cells respectively connected to a plurality of word lines, and an erase control transistor having a first end connected to at least one of both ends of plurality of memory cells and a second end connected to at least one of both ends of each of the plurality of cell strings, and a row decoder configured to apply a first bias voltage to the plurality of word lines in a first period in which an erase voltage applied to the second end of the erase control transistor increases to a target level and to apply a second bias voltage higher than the first bias voltage to at least some of the plurality of word lines in a second period after the first period.

Abstract: A device includes a first current mirror circuit including a plurality of first transistors, the plurality of first transistors including a common gate configured to receive a decoding signal according to a number of fail bits that are program-failed, a second current mirror circuit including a plurality of second transistors including a common gate configured to receive a reference current signal and a plurality of resistors respectively electrically connected to respective first terminals of the second transistors, and a comparison circuit configured to determine a compared result by comparing a first voltage corresponding to the decoding signal with respective ones of a plurality of second voltages output from the second current mirror circuit and configured to output a count signal corresponding to the compared result.

Abstract: Examples of programming circuits and methods are provided. In one example, an adjustable programming circuit comprises a first adjustable voltage divider; a second adjustable voltage divider; a first operational amplifier, wherein an output terminal of the first operational amplifier provides a first programming voltage; and a second operational amplifier, wherein the first input terminal of the second operational amplifier is coupled to the output terminal of the second operational amplifier and the first input terminal of the second operational amplifier is coupled to the second output terminal of the first adjustable voltage divider.

Abstract: The present disclosure relates to storage devices. An example storage device includes a nonvolatile memory device that includes a plurality of memory blocks, and a memory controller that controls the nonvolatile memory device. The memory controller performs a soft erase operation on a first memory block among the plurality of memory blocks, measures a first cell count by applying a first reference voltage to a plurality of first memory cells selected in advance from a plurality of memory cells of the first memory block after performing the soft erase operation, generates a first health index associated with a retention characteristic of the first memory block based on the first cell count, and performs a reliability management operation on the first memory block based on the first health index.

Abstract: A method for partial block read compensation can include receiving a read request that specifies a memory cell connected to a string of series-connected memory cells in an array of memory cells on a memory device, the string located at an intersection of a wordline and a bitline, and causing a first voltage applied to the wordline to which the specified memory cell is connected to ramp to a first predetermined value. The method can include causing a second voltage applied to the bitline to which the specified memory cell is connected to ramp to a second predetermined value, and can include comparing, using a current comparator, a current along the string with a reference current to generate an analog output signal. It can also include causing a voltage offset, based on the analog output signal, to be applied to a read voltage level during a sensing operation.

Abstract: Disclosed herein is a semiconductor memory device. Provided is the semiconductor memory device includes a first device layer storing thermal energy and a second device layer being made of a material whose electrical properties are changed by the thermal energy, wherein the first device layer stores thermal energy if a voltage is applied to the second device layer. Since the device is composed of a material that is changed electrical characteristics by heat and a material that stores heat, it may be read as a current applied to the read voltage without applying other refresh voltage. In addition, there is no leakage current flowing through the device depending on the characteristics of the device, so additional circuit elements such as transistors and selectors are not required. The device has a fast-switching mechanism but does not cause leakage current thereby not showing resistance drift due to repetitive switching.

Abstract: A circuit including: a memory cell connected to a first power supply configured to supply a first power supply voltage; a first bleeder transistor coupled between a first node of the memory cell and ground; and a second circuit coupled to a gate electrode of the first bleeder transistor and configured to supply a bleeder signal to control the first bleeder transistor in response to a drop in the first power supply voltage, wherein the first bleeder transistor is configured to discharge the memory cell in response to receiving the bleeder signal.

Abstract: Methods, systems, and devices for techniques for parallel memory cell access are described. A memory device may include multiple tiers of memory cells. During a first duration, a first voltage may be applied to a set of word lines coupled with a tier of memory cells to threshold one or more memory cells included in a first subset of memory cells of the tier. During a second duration, a second voltage may be applied to the set of word lines to write a first logic state to the one or more memory cells of the first subset and to threshold one or more memory cells included in a second subset of memory cells of the tier. During a third duration, a third voltage may be applied to the set of word lines to write a second logic state to the one or more memory cells of the second subset.

Abstract: A circuit is provided. The circuit includes an array of memory cells including a plurality of bit lines and a plurality of word lines, sensing circuits configured to sense a difference between first and second currents on respective bit lines in selected bit lines and to produce outputs for the selected bit lines as a function of the difference, and a global counter configured to continuously provide a count value to each of the sensing circuits in dependence on a clock signal. Each sensing circuit, of the sensing circuits, can produce an output in dependence on (i) the difference between the first and second currents and (ii) a stored count value received from the global counter, the count value being stored in dependence on a value of the difference between the first and second currents.

Abstract: Implementations of the present disclosure provide a memory device, an operation method thereof, and a memory system. The memory device may include a memory cell array including a plurality of blocks. The memory device may include a peripheral circuit coupled to the memory cell array. The peripheral circuit may be configured to apply a plurality of different erasure verification voltages to a selected block among the plurality of blocks after applying a first effective erasure voltage to the selected block. The peripheral circuit may be configured to determine a second effective erasure voltage applied to the selected block according to a plurality of erasure verification results corresponding to the plurality of different erasure verification voltages. The second effective erasure voltage may be greater than the first effective erasure voltage.

Abstract: A circuit comprises a plurality of bit lines, a global counter configured to provide a count value, a global reference source, a plurality of capacitors, a comparator, a storage element, and capacitor selector circuitry. The capacitor selector circuitry is configured to select, in dependence on the count value, one or more capacitors from the plurality of capacitors, and wherein the selection of the one or more capacitors is further in dependence on pre-coded codes receivable from an agent separate from the circuit, the pre-coded codes enabling specifying respective first and second sets of the plurality of capacitors as respective one or more capacitors having respective first and second capacitance values, the pre-coded codes further enabling specifying selection of the first set to be performed at an earlier time than selection of the second set, and the second capacitance value is more than the first capacitance value.

Abstract: A control circuit that reads data from a memory array including a bit line electrically connecting memory cells, includes an amplification unit that includes a read line connected to the bit line, charges the bit line via the read line during a read operation of the data, and then amplifies an electric signal of the bit line at a sense node on the read line, and an inverter that determines data stored in a memory cell selected during the data read operation on the basis of a voltage of the sense node, in which the amplification unit includes switching elements, the switching element charges the bit line on the basis of power supplied from a first power supply having a first voltage, and the switching element is turned on/off on the basis of power supplied from a second power supply having a second voltage higher than the first voltage.

Abstract: A memory apparatus is provided and includes memory cells connected to word lines and coupled to bit lines and configured to retain a threshold voltage corresponding to data states. A control means determines ones of the data states for a first set of the memory cells connected to a selected word line and for a second set of the memory cells connected to at least one neighboring word line. The control means determines which of a plurality of state groups the memory cells of the first and second sets belong according to the data states determined. The control means determines which one of a plurality of bit line voltage biases to be applied to the bit lines coupled to the memory cells of the first set during a verify operation based on a comparison of state groups of the memory cells of the first set and the second set.

Abstract: A non-volatile storage apparatus comprises a non-volatile memory divided into blocks, with each block divided into regions. Each region of a same block includes a plurality of non-volatile memory cells controlled by a separate drain side (or different type of) select line for the region such that different regions of a same block are controlled by different drain side (or different type of) select lines. The non-volatile storage apparatus is configured to concurrently program memory cells in multiple regions.

Abstract: Disclosed are a memory device and a control method thereof. The memory device may be a high-capacity and high-performance three-dimensional NAND flash memory. The control method includes the following steps. Data for performing a programming operation on a specific memory cell area is obtained. A number of memory cells in a predetermined potential state in the data are counted as a first number value. The programming operation is performed on the specific memory cell area based on the data. A read operation is performed based on a reference voltage corresponding to the predetermined potential state. A number of memory cells in the predetermined potential state in the specific memory cell area after the programming operation are counted as a second number value. Whether the specific memory cell area has program disturbances is determined based on the first number value and the second number value.

Abstract: To improve memory cell endurance and erase times for non-volatile memories, such as NAND memory, a sub-block based adaptive erase pulse is used. In a memory structure where the array is composed of blocks that have multiple sub-blocks, after applying an erase pulse to an erase selected block, one of the sub-blocks is erased verified and, if it fails to verify, the next erase pulse's duration is tuned based on the number of memory cells of that sub-block that fail to verify. If the first verified one of the sub-blocks verifies, the other sub-blocks of the erase selected block are erased verified, with the next erase pulse's duration tuned based on the number of the other sub-blocks that fail to verify.

Abstract: A memory device is provided and includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes a plurality of word line switch transistors that are electrically coupled with the plurality of word lines. Some of the word line switch transistors have a first width and some of the word line switch transistors have a second width that is different than the first width. By providing the word line switch transistors with different widths, the size of a word line switch area in the memory device can be optimized.