Abstract: A reconfigurable processor element incorporating both course and fine grained reconfigurable elements. In alternative implementations, the present invention may comprise a reconfigurable processor comprising both reconfigurable devices with fine grained logic elements and reconfigurable devices with course grained logic elements or a reconfigurable processor comprising both reconfigurable devices with fine grained elements and non-reconfigurable devices with course grained elements.

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: A storage system is disclosed for performing control to match data among cache memories corresponding to shared volumes when multiple disk controllers containing cache memories are accessing shared volumes formed in the storage device. The storage system contains a switch for switching and connecting the multiple disk controllers containing cache memories, with a disk array containing the shared volumes capable of being commonly accessed from the multiple disk controllers. The switch performs exclusive access control of the multiple disk controllers' writing on the shared volumes, and performs control to match data other than modified data among the cache memories.

Abstract: Methods and apparatuses that enable memory devices to inform graphical processing systems about the results of WRITE de-skew training. A WRITE-TRAINING mode is added to a memory device. When the WRITE-TRAINING mode is asserted the memory data mask (DM) pin is converted to an output port. Incoming WRITE data is strobed-into the memory device and the resulting data pattern is compared to a desired pattern. If the incoming WRITE data and strobed-in data match, that result is sent to the graphical processing system by setting the DM pin HIGH. If the incoming WRITE data and the strobed-in data do not match, that result is sent to the graphical processing system by setting the DM pin LOW. Beneficially, the incoming data and the desired pattern are derived from pseudo random bit sequence (PRBS) sources.

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: A method and architecture for improving the usability and manufacturing yield of a microprocessor having a large on-chip n-way set associative cache. The architecture provides a method for working around defects in the portion of the die allocated to the data array of the cache. In particular, by adding a plurality of muxes to a way or ways in the data array of an associative cache having the shorter paths to the access control logic, each way in a bank can be selectively replaced or remapped to the ways with the shorter paths without adding any latency to the system. This selective remapping of separate ways in individual banks of the set associative cache provides a more efficient way to absorb defects and allows more defects to be absorbed in the data array of a set associative cache.

Abstract: A memory subsystem controller and buffer for a computer and a second buffer for memory tag operations. The buffers are linked to the memory controller by two bidirectional data busses. The controller operates the memory subsystem by passing memory addresses to the memory subsystem data bus through the buffers. Unidirectional control interfaces between the controller and the buffers provide memory control commands to both buffers and memory tag information to the tag buffer. The controller performs read and write operations to memory, normally interleaving a plurality of read operations with a plurality of write operations. The read and write data is temporarily stored on the buffer devices while other operations are being executed to optimize the data bandwidth of the memory subsystem of the computer.

Abstract: Systems, methods, apparatus and software can utilize an extent guard to prevent modification (including relocation) of data in the storage resource while a third-party copy operation directed at the storage resource is occurring. A data transport mechanism such as a data restore application provides an extent list to the extent guard, which monitors read and/or write activity to storage resources described by the extent list. The data transport mechanism requests a data mover to perform a third-party copy operation whereby data is moved from a data source to the storage resource. If a modification attempt is made on the portion of the storage resource described by the extent list, the extent guard stalls the modification attempt until the third-party copy operation is aborted.

Abstract: Multiple matches of words in a content addressable memory are detected by identifying each match of the input word to a word in the memory, and generating a representation of a relationship OR (xi AND xj), where xi=x1, x2, . . . xN?1, xj?xi+1, xi+2, . . . xN, and x1, x2, . . . , xN are the compare results of the individual words in the memory to the input word. A representation of at least one match is identified by generating a representation of a relationship x1 OR x2 OR x3 OR . . . OR xN. The apparatus comprises a hierarchy of logic that carries a general match representation indicating at least one match between the input word and all of the memory words, and a multiple-match representation indicating multiple matches between the input word and the words in the memory.

Abstract: Computer-readable medium storing a data structure for supporting persistant storage of a set of data, the data structure including: (a) at least an oldest version of the set of data in a first memory area the first memory area including at least one first tag for uniquely identifying the oldest version, and (b) at least a most recently updated version of the set of data in a second, distinct memory area, the second memory area including at least one second tag for uniquely identifying the most recently updated version. The invention also relates to a computer arrangement including a processor and such a computer-readable medium, as well as to a method of updating sets of data having such tagged-data structures.

Abstract: An address translation unit is provided for use in a computer system. The unit contains a set of page table entries for mapping from a virtual address to a packet address. Each page table entry corresponds to one page of virtual memory, and typically includes one or more specifiers. Each specifier relates to a different portion of the page, and maps from that portion of the page to a corresponding range of packet addresses. Accordingly, the unit allows for address translation to be performed with a sub-page granularity.

Abstract: The present invention relates to a storage device which receives input of data of arbitrary data length, stores the data, and outputs the stored data in order of input. It provides a storage device capable of unloading data of arbitrary data length from data areas quickly. The storage device is equipped with a start position pointer which additionally stores the write position before the change each time a write position memorized by a write pointer is changed due to data input. When areas are freed, new read positions are determined based on saved write positions and the number of data items to be unloaded.

Abstract: An example memory quality assuring system is provided. The system may include a memory mapping logic configured to facilitate accessing memory locations and redirecting memory accessing operations. The system may also include a memory quality assurance logic configured to logically replace a first memory location with a second memory location, to initiate testing logically isolated memory locations, and to selectively logically remove tested memory locations based on the testing. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the application. It is submitted with the understanding that it will not be employed to interpret or limit the scope or meaning of the claims 37 CFR 1.72(b).

Abstract: The data processing system comprises at least one first storage system, and at least one second storage system connected to the first storage system. The second storage system receives change information identifying pre-change and post-change copy destination storage areas in a change process for changing a copy destination storage area of a target copy pair to another storage area of the second storage system; transmits the change information to the first storage system that has a copy source storage area in the target copy pair; and transmits copy information for the purpose of copying data between the pre-change and post-change copy destination storage areas. The first storage system refers to pair information identifying the copy pair, and transmits a copy of the data stored in a copy source storage area to the second storage system that has a copy destination storage area. The first storage system updates the pair information according to the change information received from the second storage system.

Abstract: A storage device can flexibly apply a dynamic load distribution and a performance expansion to an unexpected peak performance demand changing in a time sequence such as a web server and a contents delivery at the minimum cost. In the storage device, a load condition of a logical volume is measured by a performance measuring mechanism based on a data and command processing amounts transferred by a data transfer mechanism, and contents of the logical volume set in the physical volume are copied to a logical volume set in the auxiliary logical volume by a copy mechanism based on a measurement result of the performance measuring mechanism, and the logical volume set in the auxiliary physical volume copied by the copy mechanism and the logical volume set in the physical volume serving as a copy source are provided as one virtual logical volume in a host, thereby distributing a load from the host.

Abstract: Disclosed is a memory device including self-ID information. The memory device has a storage unit for storing information related to the memory device, such as a manufacturing factory, a manufacturing date, a wafer number, coordinates on a wafer and the like. Each bank of the memory device stores self-ID information related to the memory device and outputs the self-ID information out of a chip when an address is applied thereto during a test mode.

Abstract: It is aimed to detect, notify, and save an abnormal area in semiconductor memory for greatly improving reliability. An inside of semiconductor memories provided for a memory card comprises a user area, a substitution area, an area substitution information storage area, and a management area. An inside of semiconductor memories comprises a user area, a substitution area, and a management area. The user area is a data area a user can use. The substitution area is substituted when an error occurs in the user area. The area substitution information storage area stores area substitution area information. The management area stores substitution information. The information processing section performs substitution on two levels as follows. When detecting an operation indicating a symptom of failure in a semiconductor memory area, the information processing section performs area substitution during an idle state of the memory card.

Abstract: Methods and apparatus for maintaining an average erase count in a system memory of a non-volatile memory system are disclosed. According to one aspect of the present invention, a method for determining an average number of times each block of a number of blocks within a non-volatile memory of a memory system has been erased includes obtaining an erase count for each block that indicates a number of times each block has been erased. Once all the erase counts have been obtained, the erase counts are summed, and an average erase count that indicates the average number of times each block of the number of blocks has been erased is created by substantially dividing the sum by the number of blocks.

Abstract: A system for protecting a block in a destination storage device including a data mover operable to move data from a source storage device to the block, and a controller coupled to the data mover, the controller operable to detect an application write request to the block and to stall the application write request while a data move operation initiated by the data mover is terminated.

Abstract: A system, method, and computer program product are disclosed for prohibiting unauthorized access to a protected region of memory. A protected region of memory and a trusted region of memory are both specified. A call to access a location within the protected region of memory is received. An origination location of the call is then determined. In response to a determination that the origination location is within the trusted region, the call is permitted to access the protected region of memory. In response to a determination that the origination location is outside of the trusted region, the call is prohibited from accessing the protected region of memory.