Abstract: In a semiconductor device, such as an IGBT and DMOS FET, a parasitic transistor is created between a first region (drift region) and third electrode region (emitter region) of the same conductivity type on one hand and the surface portion of a second electrode region (base region) of conductivity type opposite to that of the first-mentioned conductivity type on the other hand. An interposing layer formed of, for example, an opposite conductivity type poly-Si layer is formed in a manner to partially cover the emitter region and base region. A metal electrode film is formed as a connection electrode on the whole surface of a resultant structure such that it is in ohmic contact with the base region. The interposing layer is formed of a conductive layer and interposed with the metal electrode film formed not in direct contact with the third electrode region. The interposing layer is electrically so connected as to have some extent of resistance.

Abstract: A thin film electroluminescence device is disclosed which comprises are electrode formed on a transparatent substrate, one dielectric layer formed on the electrode, an emitting layer containing Group IIIb-Vb compound as a host material and positive trivalent element ions added as a luminescence center to the host material, the other dielectric layer formed on the emitting layer, the other electrode provided on the other dielectric layer.

Abstract: A solid state radiation sensor array panel comprising a thick deposited radiation detector layer capable of generating electron-hole pairs in response to being irradiated, and a matrix array of transistors comprising source and drain electrode elements, a charge transport layer, and a dielectric layer disposed over one surface of the detector layer. Means is provided for establishing an electric field across the detector layer, which field is collapsible to establish a higher field in irradiated areas so as to establish a current path, between the source and drain electrode elements, through pixel areas of the charge transport layer. The currents passing through pixel areas are passed to a readout circuit for processing the radiation image information.

Abstract: An improved pin junction photovoltaic element which causes photoelectromotive force by the junction of a p-type semiconductor layer, an i-type semiconductor layer and an n-type semiconductor layer, characterized in that at least one of said p-type semiconductor layer and said n-type semiconductor layer comprises a p-typed or n-typed ZSnSe.sub.1-x Te.sub.x :H:M film, where M is a dopant of p-type or n-type: the quantitative ratio of the Se to the Te is in the range of from 1:9 to 3:7 in terms of atomic ratio: the amount of the H is in the range of from 1 to 4 atomic %: and said film contains crystal grain domains in a proportion of 65 to 85 vol % per unit volume; and said i-type semiconductor layer comprises a non-single crystal Si(H,F) film or a non-single crystal Si(C,Ge)(H,F) film.

Abstract: An image sensor device of the frame transfer type comprises a substrate having a first region (10) of a first n type, a second region (12) of the opposite p-type and charge transfer channels (15) as well as an arrangement of electrodes (1A . . . 1D) of charge transfer.A photosensitive layer (50) is arranged on the surface (19) of the substrate and has window regions (100, 200) in electrical contact with the channels (15) through windows (40) provided in the arrangement of electrodes, for example through electrodes (1B, 1D). Insulating strips (24) and conductive strips (30) serve to prevent the drift from one window region to the other of charges to be transferred and to evacuate the charges of a sign opposite to that of the charges to be transferred.

Abstract: A blue LED which includes a light-emitting layer having a p-n junction makes use of the superlattice structure being formed of a plurality of BP layers and Ga.sub.x Al.sub.1-x N (0.ltoreq.x.ltoreq.1) layers which are alternately stacked, with the Ga.sub.x Al.sub.1-x N (0.ltoreq.x.ltoreq.1) layers having a zinc blende type structure, or else makes use of a Ga.sub.x Al.sub.y B.sub.1-x-y N.sub.z P.sub.1-z (0.ltoreq.x, y, z.ltoreq.1 and x+y.ltoreq.1) mixed crystal layer having a zinc blende type crystal structure.

Abstract: There are disclosed a structure and a manufacturing method of a MOS-type thin-film field effect transistor composed of a substrate having an insulating main surface, a gate electrode formed on the insulating main surface to have an upper surface and a side surface at its edge, an insulating film covering at least the upper and side surfaces of the gate electrode, a semiconductor film having three continuous first, second and third portions, the first portion positioned above the upper surface of the gate electrode, the second portion being formed in contact with the insulator film at the side surface of the gate electrode and the third portion positioned above the substrate without interposing the gate electrode, a side-wall insulator formed on a part of the third portion of the semiconductor film and having a side surface contacting the second portion of the semiconductor film, and source and drain regions formed by introducing impurity atoms into the first portion and another part of the third portion of th

Abstract: A semiconductor substrate comprising: a single-crystalline semiconductor wafer substrate; a strained layer superlattice (SLS) structure layer formed on the wafer substrate; and a compound semiconductor epitaxial layer formed on the SLS structure layer. According to the present invention, the SLS structure layer consists of pairs of a first compound semiconductor thin layer and a second compound semiconductor thin layer, the first and second thin layers having the same components in a compound system having a miscibility gap, and having different compositions outside of the miscibility gap including the limit line of the miscibility gap, respectively, at a temperature higher than that of heat-treatments applied to the compound semiconductor substrate, without a decay of the SLS structure.

Abstract: A high voltage thin film transistor comprising an amorphous semiconductor charge transport layer, laterally disposed source and drain electrodes, a first control electrode with one edge laterally overlapping the source electrode and an other edge laterally spaced from the drain electrode. A source of high potential is applied to the drain electrode and a source of low potential is applied to the first control electrode in a time varying manner so as to form an accumulation channel in the charge transport layer, opposite to the first control electrode. Device performance is improved by including a second control electrode disposed in the same plane as the first control electrode and biased for preventing the formation of defects within the charge transport layer adjacent the other edge.