Patents Examined by Daniel Ko
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Patent number: 7191279Abstract: Methods of setting numerically controlled delay lines using step sizes based on a delay locked loop lock value are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: calculating an offset value for at least one NCDL; and interpolating a new offset value for the at least one NCDL, based on a change in a delay locked loop (DLL) output value from a previous DLL output value to a new DLL output value.Type: GrantFiled: December 16, 2003Date of Patent: March 13, 2007Assignee: Broadcom CorporationInventors: Sathish Kumar, Kenneth Kindsfater, Lionel D'Luna, Lakshmanan Ramakrishnan, Anand Pande
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Patent number: 7178054Abstract: A method according to one embodiment may include receiving a frame, determining a frame type of the frame, accessing a location of memory associated with the frame type, the location comprising at least one programmable data element, and checking a validity of the frame in response to data in the location of memory associated with the frame type. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.Type: GrantFiled: February 9, 2004Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Pak-Lung Seto, Devicharan Devidas
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Patent number: 7174435Abstract: First and second latch circuits store “0” and “1”, respectively, by reset. An output signal from the first latch circuit is input to the second latch circuit. Register setting data is input to the first latch circuit via a first gate that allows an input signal to pass through when the output signal from the second latch circuit is “1”, and outputs “0” when the output signal from the second latch circuit is “0”. A write signal is supplied to a memory via a second gate that allows the input signal to pass through only when the output signal from the first latch circuit is “1”. When the register setting data indicates “0”, the output signals from both the first and the second latch circuits become “0”, and until being reset, the write error protect state is maintained.Type: GrantFiled: November 19, 2003Date of Patent: February 6, 2007Assignee: Fujitsu LimitedInventors: Tetsuya Yoshida, Yoshihiko Koike, Masayoshi Kusumoto
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Patent number: 7165158Abstract: A virtualization system is introduced between a host and a storage system. An apparatus, system, and method of migrating replication includes stopping or making dormant applications on a host, or checking whether the applications are stopped or dormant. The statuses of a primary volume and a secondary volume that is a replica of the primary volume are checked to determine whether they have become identical. A primary virtual volume is defined to map to the primary volume and a secondary virtual volume is defined to map to the secondary volume. Replication is defined from the primary virtual volume to the secondary virtual volume. Replication is started with a NOCOPY option, and the applications may be restarted or a message is sent indicating that the applications can be restarted. There is no actual migration of application data, and as result, the time required for migrating replication can be eliminated.Type: GrantFiled: August 17, 2005Date of Patent: January 16, 2007Assignee: Hitachi, Ltd.Inventor: Yuichi Yagawa
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Patent number: 7162602Abstract: A storage system, method and system for protecting data stored on a volume of the storage system. The storage system includes a storage media upon which the volume is represented, a disk controller which controls the storage system, and a write once read many (WORM) configuration table having a plurality of entries which indicate by use of a next write pointer which of a plurality of areas of the volume is write protected. Alternatively, the entries of the WORM configuration table could indicate write protected areas of the volume each being defined by use of a beginning offset and an ending offset.Type: GrantFiled: March 16, 2004Date of Patent: January 9, 2007Assignee: Hitachi, Ltd.Inventor: Shoji Kodama
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Patent number: 7149873Abstract: In one embodiment of the invention, a method is provided to allow an operating system to support both address space layouts of a SAS OS and a MAS OS at the same time, with the choice of which layout type to be used to be made by the application developer. In one embodiment the method includes: selecting one of a mostly private address space (MPAS) model and a mostly global address space (MGAS) model, where if the MPAS model is selected, then a process is permitted to map a shared object in a mostly private address space (MPAS) layout so that the process perceives a behavior as if the process is running on a multiple address space operating system, and where if the MGAS model is selected, then the process is permitted to map a shared object in a mostly global address space (MGAS) layout so that the process perceives a behavior as if the process is running on a single address space operating system.Type: GrantFiled: October 24, 2003Date of Patent: December 12, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Saleem Mohideen, Manish Ahluwalia
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Patent number: 7146475Abstract: Users of Mainframe computers running under IBM's MVS operating systems have a need to merge migrate data from multiple smaller DASD devices (disk volumes) to larger DASD devices, and/or to migrate data in order to combine data set extents. A method is disclosed for migrating data where a volume merge is involved, and/or when combining of extents is desired, that minimizes the down time of applications using the involved data while satisfying MVS rules for volume and catalog meta-data files as well as data extent limitations. The method may be implemented such that source and target volumes need not be in like manufacturer DASD devices.Type: GrantFiled: November 18, 2003Date of Patent: December 5, 2006Assignee: Mainstar Software CorporationInventor: Robert M. Perego
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Patent number: 7146456Abstract: A dynamic random access memory device is capable of converting from a full density memory device to a reduced density memory device. The reduced density memory device compensates for cell failures in a plurality of cell blocks, regardless of the location of the cell failures. The memory device includes a row address mapping fuse for selectively determining row address combinations capable of storing data bits. A row address mapping logic is coupled to the row address mapping fuse and is capable of routing data bits to the address combinations capable of storing data bits.Type: GrantFiled: September 29, 2003Date of Patent: December 5, 2006Assignee: Infineon Technologies North America Corp.Inventor: Jungwon Suh
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Patent number: 7124261Abstract: A data processing system 2 has a base data address region 24 and a bit-band data address region 28. Memory accesses to the bit-band data address region 28 are converted into memory accesses to the base data address region 24. In the process of this conversion specific bits within the base data address region 24 are picked out for access whether that be via a read-modify-write operation or a masked read operation as appropriate. In this way, bit access is provided to data values within the base data address region 24 by addressing specific address locations within the bit-band data address region 28.Type: GrantFiled: February 9, 2004Date of Patent: October 17, 2006Assignee: ARM LimitedInventors: Paul Kimelman, Ian Field
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Patent number: 7120737Abstract: A disk drive is disclosed including a disk having a plurality of tracks, wherein each track comprises a plurality of data sectors. A microprocessor executes a write command associated with a disk command data structure by inserting the disk command data structure into a dirty queue, and then executing the write command using the disk command data structure by writing data blocks to a plurality of target data sectors. The disk command data structure is then inserted into a write verify queue, and the disk command data structure is used to perform a write verify operation. The disk command data structure is inserted into an available queue if the target data sectors pass the write verify operation, and the disk command data structure is inserted back into the dirty queue if at least one of the target data sectors fails the write verify operation.Type: GrantFiled: January 20, 2006Date of Patent: October 10, 2006Assignee: Western Digital Technologies, Inc.Inventor: Gregory B. Thelin
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Patent number: 7111111Abstract: Methods of optimizing a plurality of numerically controlled delay lines (NCDLS) in a DDR memory controller are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: acquiring a plurality of statistics, the plurality of statistics defining an operating region for the DDR memory controller; and calculating optimal values for the plurality of NCDLs, the optimal values calculated using the plurality of statistics.Type: GrantFiled: November 18, 2003Date of Patent: September 19, 2006Assignee: Broadcom CorporationInventors: Darren Neuman, Sathish Kumar Radhakrishnan, Jeffrey Fisher, Joshua Stults, Nitin Borle, Kaushik Bhattacharya
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Patent number: 7107404Abstract: A data processing system comprising a storage apparatus and computers which executes a first program and a second program, the storage apparatus having a cache memory with a first area and a second area and a disk unit for storing data of the cache memory. The storage apparatus writes data into the first area corresponding to area identification information included in a data storage request in response to an input of the data storage request. The data is written into the second area corresponding to area identification information included in a data storage request in response to an input of the data storage request. The data stored in the second area is copied to the first area in response to an input of a copy request for causing the data in the second area to be reflected in the first area.Type: GrantFiled: September 2, 2004Date of Patent: September 12, 2006Assignee: Hitachi, Ltd.Inventors: Kouichi Ohtsubo, Nobuo Kawamura
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Patent number: 7103721Abstract: An improved method and apparatus for selecting invalid members as victims in a least recently used cache system. An invalid cache line selection unit has an input connected to a cache directory and an output connected to a most recently used update logic. In response to a miss in the cache, an invalid cache line is identified from information in the cache directory by the invalid cache line selection unit. This invalid cache line is updated to be the next victim by the most recently used update logic, rather than attempting to override the current victim selection by a least recently used victim selection logic. The next victim also may be selected in response to a cache hit in which information from the cache directory also is read.Type: GrantFiled: April 28, 2003Date of Patent: September 5, 2006Assignee: International Business Machines CorporationInventors: Robert Alan Cargnoni, Guy Lynn Guthrie, William John Starke, Jeffrey Adam Stuecheli
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Patent number: 7100018Abstract: A system and method for encoding page size information has been described herein. In one embodiment, the method includes determining whether a virtual address is stored in a translation lookaside buffer (TLB), the TLB including a plurality of entries, wherein the entries include a minimum virtual page number bit string and a variable bit string. In one embodiment the method also includes determining whether the first bit string matches the minimum virtual page number bit string of one of the entries. In one embodiment, if the first bit string matches the minimum virtual page number bit string of one of the entries, the method includes decoding a page size stored in the variable portion of the matching entry and a 1-bit field associated with the matching entry, wherein the decoding determines a set of bits of the variable bit string.Type: GrantFiled: July 31, 2003Date of Patent: August 29, 2006Assignee: Silicon Graphics, Inc.Inventors: David Zhang, Mahdi Seddighnezhad
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Patent number: 7099994Abstract: Embodiments of the present invention are broadly directed to a memory system. In one embodiment, a first data memory is coupled to a first memory controller and a second data memory is coupled to a second memory controller. A parity memory is coupled to a parity controller, the parity controller being directly coupled to both the first memory controller and the second memory controller. Parity data control logic is configured to store and retrieve parity information associated with data stored in both the first data memory and the second data memory, the parity data control logic configured to interleave within the parity memory parity data associated with data stored in the first data memory with parity data associated with data stored in the second data memory.Type: GrantFiled: September 29, 2003Date of Patent: August 29, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Larry Thayer, Eric McCutcheon Rentschler, Michael Kennard Tayler
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Patent number: 7089384Abstract: A method for managing a data storage system includes maintaining a record predictive of locations to which data are to be written on a first storage medium by a host computer. Upon receiving a write command from the host computer directed to storing specified data at a specified location on the first storage medium, if the specified location is not included in the record, the record is updated responsively to the specified location. A signal is sent to the host computer that the specified data have been stored in the data storage system responsively to storing the specified data and, if the specified location was not included in the record, responsively to updating the record. The specified data are copied to the second storage medium responsively to the record, and are stored in the specified location on both the first and second storage media.Type: GrantFiled: December 29, 2003Date of Patent: August 8, 2006Assignee: International Business Machines CorporationInventors: Martin Tross, Aviad Zlotnick
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Patent number: 7085904Abstract: A storage system includes a disk controller and a disk device having original volumes for backup and a storage pool for backup data. It incorporates a differential management program which checks whether the original volumes for backup are updated or not; a pool management program which allocates a disk area to the storage pool for backup data; a performance management program which manages the performance of each volume; and a backup control program which performs total backup control. A backup method by which recovery within a user-specified recovery object time is possible is selected according to the restore performance calculated by the performance management program and the total size of changed blocks after backup acquisition as counted by the differential management program.Type: GrantFiled: February 20, 2004Date of Patent: August 1, 2006Assignee: Hitachi, Ltd.Inventors: Yoichi Mizuno, Naoto Matsunami, Ikuya Yagisawa
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Patent number: 7085902Abstract: A method for managing a data storage system includes copying data stored on a first storage subsystem to a second storage subsystem in an asynchronous mirroring process. A record is maintained on the second storage subsystem, indicative of locations at which the data have been updated on the first storage subsystem and have not yet been copied to the second storage subsystem. Upon receiving at the second storage subsystem, from a host processor, a request to access the data stored at a specified location on the data storage system, if the specified location is included in the record, the second storage subsystem initiates a synchronous transfer of the data at the specified location from the first storage subsystem.Type: GrantFiled: September 29, 2003Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Amiram Hayardeny, Avi Teperman, Martin Tross, Aviad Zlotnick
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Disk drive executing a preemptive multitasking operating system comprising tasks of varying priority
Patent number: 7082494Abstract: A disk drive is disclosed for executing a preemptive multitasking operating system comprising tasks of varying priority, including a disk task for processing disk commands by initiating seek operations and configuring parameters of a read/write channel, a host task for initiating disk commands in response to host commands received from a host computer, a background task for initiating disk commands to perform background operations including a defect scan of the disk, and an execution task for arbitrating the disk commands generated by the host task and the background task and for transmitting the arbitrated disk commands to the disk task.Type: GrantFiled: December 24, 2002Date of Patent: July 25, 2006Assignee: Western Digital Technologies, Inc.Inventors: Gregory B. Thelin, Michael S. Rothberg, Eric L. Severtson, John Edward Lauber, Horia Cristian Simionescu -
Patent number: 7076621Abstract: A storage control apparatus and a storage control method are provided wherein in a system having a plurality of disk systems and secondary disk systems at remote sites, the data transfer amount between a central processing unit and a disk system can be reduced when duplicate disk write is performed, the performance can be prevented from being degraded even if the distance between control units is elongated, and the intermediate results of a transaction are not left. A standard time is determined and a program is provided which instructs a secondary central processing unit to reflect only update information having a write time older than the standard time, upon a logical disk in the secondary disk system.Type: GrantFiled: August 31, 2004Date of Patent: July 11, 2006Assignee: Hitachi, Ltd.Inventors: Kenta Ninose, Hiroshi Arakawa, Yoshihiro Asaka, Yusuke Hirakawa