Abstract: A multispectural superconductive quantum radiant energy detector and related method utilizing a closed loop of superconductive material having spaced legs, one of which is disposed to ambient. The superconductivity current is divided in the first and second legs according to geometric and kinetic inductances. A ground plane is provided for minimizing the geometric inductance with the loop during injection and removal of the current.

Abstract: A Josephson junction consisting of high temperature ceramic superconductors layers, separated by an ultra-thin insulating barrier made of an non oxide substance like diamond-like carbon, is described. An integral part of this disclosure is the technique involving the use of an activated oxygen species for providing an oxygen chemical potential which is higher than that obtainable at barometric pressure. Also clarified are the structure and method of manufacturing the said junction, using high temperature superconductors.

Abstract: A light emitting device having: a first GaAlAs clad layer of a first conductivity type having a first AlAs mixed crystal ratio, the first GaAlAs clad layer serving as a first layer of the device; a GaAlAs active layer having a second AlAs mixed crystal ratio different from the first AlAs mixed crystal ratio, the second AlAs mixed crystal ratio being set to a value necessary for light emission wavelength within a range of 610 nm to 640 nm, the GaAlAs active layer serving as a second layer of the device; and a second GaAlAs clad layer of a second conductivity type having a third AlAs mixed crystal ratio different from the second AlAs mixed crystal ratio, the second GaAlAs clad layer serving as a third layer of the device, wherein the GaAlAs active layer of the first conductivity type serving as said second layer is sandwiched between the first GaAlAs clad layer of the first conductivity type serving as the first layer and the second GaAlAs clad layer of the second conductivity type serving as the third layer, t

Abstract: A semiconductor chip package comprising at least one semiconductor chip disposed in a package and a plurality of first and second pins extending from the package, which first pins are electrically connected to the at least one semiconductor chip and are adapted to conduct signals between the at least one semiconductor chip and external circuitry, the first pins being divided into a plurality of groups, each group representing a respective signal type, and which second pins are not electrically connected to the at least one semiconductor chip, the first pins of at least one group and the second pins being asymmetrically disposed along edges of the package and the remaining groups of first pins being symmetrically disposed along edges of the package. The invention also provides a stacked module of the semiconductor chip package.

Abstract: An apparatus for responding to incident electromagnetic radiation includes a first medium having a surface and through which incident electromagnetic radiation may be transmitted, a second such medium having a surface, the surfaces being generally parallel, and smectic liquid crystal between said surfaces and aligned generally in parallel in layers that extend generally parallel to each other and perpendicularly to such surfaces (bookshelf alignment), the liquid crystal material being operative to undergo self-focusing in response to a characteristic of incident electromagnetic radiation exceeding a value and being cooperative with at least one of such media thereby automatically to limit the energy or energy density of electromagnetic radiation exiting the apparatus.

Abstract: A source diffusion region and a drain diffusion region are formed under an insulation film which is thicker than a gate insulation film and which isolates the adjacent channel regions from each other. The adjacent source and drain diffusion regions are isolated from each other by a trench which extends from the central portion of the thick insulation film to the interior of a semiconductor substrate. The trench is formed in a self-alignment manner with reference to the end portions of the adjacent floating gate electrodes, and the depth of this trench is determined so that the adjacent source and drain diffusion regions can be spaced sufficiently apart from each other. Since the trench reliably prevents punch-through and current leakage to the adjacent element, it is possible to remarkably reduce the cell size. Moreover, the peripheral circuits are not complicated since the functions of the source and drain regions are fixed.

Abstract: Method for displaying levels of greys on a matrix display screen, such as a chiral smectic phase ferroelectric liquid crystals screen, comprising a cell containing the crystal provided on its walls with two matrix systems of right angle i line conductors and j column conductors, the various pixels of the image being defined by the superimposed crossings of these conductors, wherein each pixel is embodied with the aid of p independent sub-pixels each having its own transmission coefficient, each of which is able to display several states of different basic greys, including black and white, and, on each of the p sub-pixels, one of the states of the preceding greys is displayed by taking account, for each of these, of its own transmission so as to obtain for each pixel via the visual addition of the contributions of each sub-pixel the display of a suitable shade of grey closest to the analog value indicated by the video write signal.

Abstract: A lateral thyristor is provided which includes a semiconductor substrate of a first conductivity type, an epitaxial layer of a second conductivity type formed on the semiconductor substrate, an anode diffusion layer of the first conductivity type formed in the epitaxial layer, a gate diffusion layer of the first conductivity type formed in the epitaxial layer, and a buried layer of the second conductivity type formed below the anode diffusion layer and extending between the semiconductor substrate and the epitaxial layer, wherein there is a region directly below the anode diffusion layer where the anode diffusion layer and the buried layer do not overlap each other, when the lateral thyristor is looked down upon in a direction perpendicular to the principal surface of the semiconductor substrate.

Abstract: An enhanced conductivity structure comprising first and second coupled quantum well channel layers spaced from each other by a barrier layer of predetermined thickness is provided. The barrier layer and other supporting layers comprise a first material type, while the first and second quantum wells comprise a second material type having a narrower bandgap than the first material type. Each of the quantum wells is thin to confine current flow to the plane of the quantum wells. First and second spacer layers of the first material type are formed adjacent to each of the quantum wells, and planar doping layers are provided on each of the spacer layers. First and second buffer layers of the first material type are formed adjacent to each of the spacer layers.

Abstract: A beam (e.g. a focused laser beam) is utilized to irradiate the entire lateral width of a limited-extent portion of an elongated superconducting thin-film lead. The irradiated portion is converted to be non-superconducting and photoconductive. The converted portion constitutes a photodetector integrated with associated superconducting leads.

Abstract: A quasi one-dimensional electron gas FET with semiconductor layer of a stripe structure formed on a semi-insulating semiconductor substrate. A gate electrode is formed traversing the exposed portions of the semiconductor substrate and the side faces and the upper face of the stripe structure, and a source electrode and a drain electrode are formed on the respective ends of the stripe structure with the gate electrode in between. The stripe structure consists of a potential barrier layer, an undoped channel layer and an electron supplying layer.

Abstract: A microbridge superconductor device includes a substrate, made of a material such as LaAlO.sub.3, having a lower planar substrate surface, an inclined surface having an overall upward inclination of from about 20 to about 80 degrees from the plane of the lower planar substrate surface, and an upper planar substrate surface parallel to the lower planar substrate surface and separated from the lower planar substrate surface by the inclined surface. A layer of a c-axis oriented superconductor material, made of a material such as YBa.sub.2 Cu.sub.3 O.sub.7-x, is epitaxially deposited on the lower planar substrate surface, and has an exposed a-axis edge adjacent the intersection of the lower planar substrate surface with the inclined surface. The a-axis exposed edge is beveled away from the intersection. A layer of a c-axis oriented superconductor material is epitaxially deposited on the upper planar substrate surface, and has an exposed a-axis edge adjacent the inclined surface.

Abstract: A high power density semiconductor module of reduced size and weight wherein a fusion element assembly for meeting electrical power processing requirements is nested in a hollow casing for both electrically insulating and operatively cooling by a single fluid medium. A pair of electrically conductive terminals penetrates the casing at opposite ends to make an electrical path through the fusion element assembly which resides within the casing as a stack in which each semiconductor fusion element is interleaved with plural heat sink elements undergoing a uniform compressive loading parameter. The stack is electrically insulated and cooled through transverse grooves in the fusion element assembly, which in one embodiment for space based utilization, is by way of finned heat sink or backing plate elements for passaging a dual function cryogen fluid such as supercritical liquid hydrogen.

Abstract: Disclosed is a Hall effect element formed in a single crystal semiconductor chip with the direction of bias current flow aligned parallel with the <100> cyrstallographic direction and also parallel with edges of the chip. The orientation described is selected to minimize piezoresistive effects produced by packaging-induced physical stress on the semiconductor chip.

Abstract: A semiconductor structure includes a compound semiconductor substrate, a compound semiconductor diffusion limiting layer containing aluminum, disposed on the substrate, and having a larger aluminum content than the substrate, a compound semiconductor layer disposed on the diffusion limiting layer, a silicon film disposed on the semiconductor layer, and a diffusion region into which silicon has diffused from the silicon film to reach the interface between the diffusion limiting layer and the substrate. The diffusion limiting layer may be employed in a semiconductor laser to prevent silicon from diffusing beyond desired regions and to form a light-confining structure.

Abstract: A conductor attachment wherein each conductor is mounted on a dielectric tape and has an attachment portion that is supported by the tape to an adjacent location a uniform distance from the bonding location and that contacts on a level with the plane of the underside of the tape. One conductor supporting tape has portions of the tape that extend into a central contacting area opening to contact locations at contacting pads in rows remote from the edge. Another supporting tape has window openings at the contacting locations. The conductor ends are brought into the level of the underside of the tape by a manufacturing rolling operation between an elastomer surface roller and a solid backing roller.

Abstract: An electro-optical device with a transparent substrate is produced by epitaxially first growing the active device layers, followed by growth of the transparent substrate layer on an opaque wafer. The opaque wafer is subsequently removed. The active device layers have dopants with sufficiently low diffusivities that their electronic characteristics are not adversely affected by long exposure to elevated temperature during the growth of the transparent substrate layer. In a liquid phase epitaxy (LPE) method, a repeated temperature cycle technique is used where the temperature is repeatedly raised each time after cooling to provide a large cooling range for growing a sufficiently thick substrate layer or a series of device layers. In between growths and during the temperature heat-up periods, the device is stored within the LPE reactor. When a epitaxial layer is oxidizable, a non-oxidizable cap is temporarily grown on it in between growths and during the temperature heat up periods.

Abstract: A silicon on insulator of integrated circuit comprising a plurality of components typically adopted for high voltage application having a semiconductor substrate of a first conductivity type, an insulating layer provided on the substrate, a semiconductor layer provided on the insulating layer, a number of laterally separated circuit elements forming parts of a number of subcircuits provided in the semiconductor layer, a diffusion layer of a second conductivity type opposite to that of the first conductivity type provided in the substrate and laterally separated from all the other circuit elements and means for holding the diffusion layer at a voltage at least equal to that of the highest potential of any of the subcircuits present in the integrated device.

Abstract: A device made with thin layers comprises at least two layers of materials having different electrical characteristics. At least one of the layers is superconductive. The superconductive layer comprises a rare earth (or yttrium) which is chosen so as to confer superconductive characteristics. The other layer has a constitution which differs from that of the superconductive layer, solely by the fact that the rare earth is different and confers different electrical properties.

Abstract: A charge transfer device is fabricated on a semiconductor substrate of a first conductivity type and comprises a well formed in a surface portion of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type, a charge transfer region of the first conductivity type formed in a surface portion of the well, a floating diffusion region of the first conductivity type formed in the surface portion of the well and contiguous to the charge transfer region, an insulating film covering the surface portion of the well, and a plurality of gate electrodes provided on the insulating film and applied with driving clocks in such a manner as to produce conductive channels in the charge transfer region for transferring electric charges toward the floating diffusion region, in which the channels in the vicinity of the floating diffusion region are gradually decreased in width toward the floating diffusion region, and in which impurity atoms of the well beneath the charge transfer r