Patents Examined by Daniel Pan
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Patent number: 9817670Abstract: When a main processor issues a command to co-processor, a timeout value is included in the command. As the co-processor attempts to execute the command, it is determined whether the attempt is taking time beyond what is permitted by the timeout value. If the timeout is exceeded then responsive action is taken, such as the generation of a command timeout type failure message. The receipt of the command with the timeout value, and the consequent determination of a timeout condition for the command, may be determined by: the co-processor that receives the command, or a watchdog timer that is separate from the co-processor. Also, detection of co-processor hang and/or hung co-processor conditions during the time that a co-processor is executing a command for the main processor.Type: GrantFiled: December 13, 2013Date of Patent: November 14, 2017Assignee: International Business Machines CorporationInventors: Nitin Gupta, Mehulkumar J. Patel, Deepak C. Shetty
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Patent number: 9811385Abstract: An electronic device includes a processing component and a task manager. The processing component is configurable for one of a single-core processing mode and a multi-core processing mode. The task manager determines a number of tasks running on the electronic device. The processor is configured to switch between either the single-core processing mode or the multi-core processing mode as a function of the number of tasks.Type: GrantFiled: April 28, 2010Date of Patent: November 7, 2017Assignee: WIND RIVER SYSTEMS, INC.Inventors: Maarten Koning, Stephen Li
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Patent number: 9804842Abstract: An apparatus and method for efficiently managing the architectural state of a processor.Type: GrantFiled: December 23, 2014Date of Patent: October 31, 2017Assignee: INTEL CORPORATIONInventors: Jesus Corbal San Adrian, Dennis R. Bradford, Benjamin C. Chaffin, Taraneh Bahrami, Jonathan C. Hall, Thomas B. Maciukenas, Roger Gramunt, Rohan Sharma
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Patent number: 9792112Abstract: A microprocessor includes a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode. A first core of the plurality of processing cores is configured to encounter an instruction that instructs the first core to apply a microcode patch. The first core of the plurality of processing cores is further configured to, in response to encountering the instruction, inform each core of the other of the plurality of processing cores of the microcode patch and apply the microcode patch to the hardware of the first core. Each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to the hardware of the core, in response to being informed by the first core.Type: GrantFiled: May 19, 2014Date of Patent: October 17, 2017Assignee: VIA TECHNOLOGIES, INC.Inventors: G. Glenn Henry, Stephan Gaskins
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Patent number: 9785435Abstract: An instruction to perform a comparison of a first value and a second value is executed. Based on a control of the instruction, a compare function to be performed is determined. The compare function is one of a plurality of compare functions configured for the instruction, and the compare function has a plurality of options for comparison. A compare option based on the first value and the second value is selected from the plurality of options defined for the compare function, and used to compare the first value and the second value. A result of the comparison is then placed in a select location, the result to be used in processing within a computing environment.Type: GrantFiled: October 27, 2016Date of Patent: October 10, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan D. Bradbury, Michael K. Gschwind, Silvia Melitta Mueller, Brett Olsson, Eric M. Schwarz
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Patent number: 9766886Abstract: Instructions and logic provide vector linear interpolation functionality. In some embodiments, responsive to an instruction specifying: a first operand from a set of vector registers, a size of each of the vector elements, a portion of the vector elements upon which to compute linear interpolations, a second operand from a set of vector registers, and a third operand; an execution unit, reads a first, a second and a third value of the size of vector elements from corresponding data fields in the first, the second and the third operand respectively and computes an interpolated value as the first value multiplied by the second value minus the second value multiplied by the third value plus the third value.Type: GrantFiled: December 16, 2011Date of Patent: September 19, 2017Assignee: Intel CorporationInventors: Jesus Corbal, Andrew T. Forsyth, Lisa K. Wu, Thomas D. Fletcher
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Patent number: 9747197Abstract: A method for using an access triggered architecture for a computer implemented application is provided. The method receives a set of data at a designated functional block associated with a system memory location; performs an operation at the designated functional block, using the set of data, to generate a result, wherein the operation is performed each time information is received at the designated functional block; and returns the generated result to the system memory location.Type: GrantFiled: May 20, 2014Date of Patent: August 29, 2017Assignee: HONEYWELL INTERNATIONAL INC.Inventors: Thom Kreider, Jon Douglas Gilreath, Gary Warnica
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Patent number: 9747106Abstract: The disclosure herein provides systems, methods, and computer program products for managing a plurality of operands in a computer instruction. To manage the plurality of operands, a data buffer manager executed by a processor receives information from a caller. The information relates to the plurality of operands. The data buffer manager, also, compares a free data area size to a requested minimum data area of an operand size identified by the information; selects an address when the requested minimum data area is less than or equal to the free data area size; and inserts the operand at the address.Type: GrantFiled: September 30, 2016Date of Patent: August 29, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Louis P. Gomes
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Patent number: 9740659Abstract: Methods, systems, and articles of manufacture for merging and sorting arrays on a processor are provided herein. A method includes splitting an input array into multiple sub-arrays across multiple processing elements; merging the multiple sub-arrays into multiple vectors; and sorting the multiple vectors by comparing and swapping one or more vector elements among the multiple vectors.Type: GrantFiled: March 19, 2014Date of Patent: August 22, 2017Assignee: International Business Machines CorporationInventors: Dheeraj Sreedhar, Robert Montoye, Jeffrey H. Derby
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Patent number: 9727526Abstract: A reconfigurable vector processor is described that allows the size of its vector units to be changed in order to process vectors of different sizes. The reconfigurable vector processor comprises a plurality of processor units. Each of the processor units comprises a control unit for decoding instructions and generating control signals, a scalar unit for processing instructions on scalar data, and a vector unit for processing instructions on vector data under control of control signals. The reconfigurable vector processor architecture also comprises a vector control selector for selectively providing control signals generated by one processor unit of the plurality of processor units to the vector unit of a different processor unit of the plurality of processor units.Type: GrantFiled: January 25, 2011Date of Patent: August 8, 2017Assignee: NXP USA, Inc.Inventors: Malcolm Stewart, Ali Osman Ors, Daniel Laroche
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Patent number: 9720696Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.Type: GrantFiled: September 30, 2014Date of Patent: August 1, 2017Assignee: International Business Machines CorporationInventors: Sam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto
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Patent number: 9710279Abstract: An apparatus and method for speculative vectorization. For example, one embodiment of a processor comprises: a queue comprising a set of locations for storing addresses associated with vectorized memory access instructions; and execution logic to execute a first vectorized memory access instruction to access the queue and to compare a new address associated with the first vectorized memory access instruction with existing addresses stored within a specified range of locations within the queue to detect whether a conflict exists, the existing addresses having been previously stored responsive to one or more prior vectorized memory access instructions.Type: GrantFiled: September 26, 2014Date of Patent: July 18, 2017Assignee: Intel CorporationInventors: Nalini Vasudevan, Cheng Wang, Youfeng Wu, Albert Hartono, Sara S. Baghsorkhi
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Patent number: 9712614Abstract: This invention relates to a communication system including a first apparatus having a first storage medium, and a second apparatus for transmitting data to the first apparatus, the second apparatus comprising: a second storage medium for storing management information of data to be transferred to the first storage medium; communication means for communicating data with the first apparatus; edit means capable of editing the management information; and control means for making a control to transfer data stored in the second storage medium to the first storage medium by way of the communication means on the basis of the management information edited by the edit means.Type: GrantFiled: March 28, 2014Date of Patent: July 18, 2017Assignee: Data Scape, Ltd.Inventor: Akihiro Morohashi
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Patent number: 9703558Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.Type: GrantFiled: December 23, 2011Date of Patent: July 11, 2017Assignee: Intel CorporationInventors: Victor W. Lee, Daehyun Kim, Tin-Fook Ngai, Jayashankar Bharadwaj, Albert Hartono, Sara Baghsorkhi, Nalini Vasudevan
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Patent number: 9696998Abstract: The apparatuses, systems, and methods in accordance with the embodiments disclosed herein may facilitate modifying post silicon instruction behavior. Embodiments herein may provide registers in predetermined locations in an integrated circuit. These registers may be mapped to generic instructions, which can modify an operation of the integrated circuit. In some embodiments, these registers may be used to implement a patch routine to change the behavior of at least a portion of the integrated circuit. In this manner, the original design of the integrated circuit may be altered.Type: GrantFiled: August 29, 2013Date of Patent: July 4, 2017Assignee: Advanced Micro Devices, Inc.Inventor: Frank C Galloway
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Patent number: 9690586Abstract: A method of managing instruction execution for multiple instruction streams using a processor core having multiple parallel instruction execution slices provides instruction processing flexibility. An event is detected indicating that either resource requirement or resource availability for a subsequent instruction of an instruction stream will not be met by the instruction execution slice currently executing the instruction stream. In response to detecting the event, dispatch of at least a portion of the subsequent instruction is made to another instruction execution slice. The event may be a compiler-inserted directive, may be an event detected by logic in the processor core, or may be determined by a thread sequencer. The execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution, ordinary instruction execution, wide instruction execution.Type: GrantFiled: June 12, 2014Date of Patent: June 27, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lee Evan Eisen, Hung Qui Le, Jentje Leenstra, Jose Eduardo Moreira, Bruce Joseph Ronchetti, Brian William Thompto, Albert James Van Norstrand, Jr.
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Patent number: 9690620Abstract: Methods and architecture for dynamic polymorphic heterogeneous multi-core processor operation are provided. The method for dynamic heterogeneous polymorphic processing includes the steps of receiving a processing task comprising a plurality of serial threads. The method is performed in a processor including a plurality of processing cores, each of the plurality of processing cores being assigned to one of a plurality of core clusters and each of the plurality of core clusters capable of dynamically forming a coalition comprising two or more of its processing cores. The method further includes determining whether each of the plurality of serial threads requires more than one processing core, and sending a go-into-coalition-mode-now instruction to ones of the plurality of core clusters for handling ones of the plurality of serial threads that require more than one processing core.Type: GrantFiled: December 3, 2012Date of Patent: June 27, 2017Assignee: National University of SingaporeInventors: Tulika Mitra, Mihai Pricopi
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Patent number: 9690585Abstract: A method of operation of a processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues coupled by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the relationship between the slices and instruction streams according to execution requirements for the instruction streams and the availability of resources in the instruction execution slices. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution and ordinary instruction execution on a per-instruction basis. Instructions having an operand width greater than the width of a single instruction execution slice may be processed by multiple instruction execution slices configured to act in concert for the particular instructions.Type: GrantFiled: June 10, 2014Date of Patent: June 27, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lee Evan Eisen, Hung Qui Le, Jentje Leenstra, Jose Eduardo Moreira, Bruce Joseph Ronchetti, Brian William Thompto, Albert James Van Norstrand, Jr.
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Patent number: 9678758Abstract: Systems and methods for implementing certain load instructions, such as vector load instructions by cooperation of a main processor and a coprocessor. The load instructions which are identified by the main processor for offloading to the coprocessor are committed in the main processor without receiving corresponding load data. Post-commit, the load instructions are processed in the coprocessor, such that latencies incurred in fetching the load data are hidden from the main processor. By implementing an out-of-order load data buffer associated with an in-order instruction buffer, the coprocessor is also configured to avoid stalls due to long latencies which may be involved in fetching the load data from levels of memory hierarchy, such as L2, L3, L4 caches, main memory, etc.Type: GrantFiled: September 26, 2014Date of Patent: June 13, 2017Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, Christopher Edward Koob, Eric Wayne Mahurin, Suresh Kumar Venkumahanti
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Patent number: 9672043Abstract: Techniques for managing instruction execution for multiple instruction streams using a processor core having multiple parallel instruction execution slices provide flexibility in execution of program instructions by a processor core. An event is detected indicating that either resource requirement or resource availability will not be met by the execution slice currently executing the instruction stream. In response to detecting the event, dispatch of at least a portion of the subsequent instruction is made to another instruction execution slice. The event may be a compiler-inserted directive, may be an event detected by logic in the processor core, or may be determined by a thread sequencer. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution, ordinary instruction execution, wide instruction execution.Type: GrantFiled: May 12, 2014Date of Patent: June 6, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lee Evan Eisen, Hung Qui Le, Jentje Leenstra, Jose Eduardo Moreira, Bruce Joseph Ronchetti, Brian William Thompto, Albert James Van Norstrand, Jr.