Abstract: A method and apparatus for adjusting a bandwidth of a sigma delta converter by adjusting a reference voltage provided to the sigma delta converter. The apparatus includes a switched capacitor digital-to-analog converter in the feedback loop of the sigma delta modulator. The sigma delta modulator determines the bandwidth mode of the converter and adjusts the reference voltage to deliver high performance functionality. In one embodiment, a multi-bit digital signal is received by the digital-to-analog converter. The reference voltage is provided to multiple capacitive circuits of the digital-to-analog converter and the capacitive circuits are activated and deactivated based on the multi-bit digital signal. The digital-to-analog converter, thus, provides a feedback analog signal using dynamic element matching.

Abstract: A radio communications system includes a transmitter and a receiver. The transmitter generates or receives digital symbols having a given symbol rate associated with a corresponding symbol period; and generates, every S digital symbols generated/received (S>3), a respective multi-mode digital signal, which has a predefined time length shorter than S times the symbol period, which is sampled with a predefined sampling rate higher than the symbol rate, and which carries the S digital symbols by a plurality of orthogonal harmonic modes including a main mode which is a real harmonic mode and carries P of the S digital symbols (P<S). The receiver receives and processes the radio frequency signal to obtain a corresponding incoming digital signal; and extracts, from successive, non-overlapped portions of the incoming digital signal sampled with the predefined sampling rate, the S digital symbols respectively carried by each incoming digital signal portion by the orthogonal harmonic modes.

Abstract: A technique for assessing the reliability of bits received by a modulation symbol on a channel is provided. A providing circuit provides an input dataset including a plurality of input values. The input values correspond to different transmit hypotheses according to a modulation alphabet used for encoding the bits in the symbol. A computing circuit performs a first computing step and a second computing step. In the first computing step, a first intermediary dataset is computed by combining the input values of the input dataset according to a first combination scheme. In the second computing step, a second intermediary dataset is computed by combining the input values of the input dataset according to a second combination scheme. The second combination scheme is different from the first combination scheme. An assessing circuit assesses the reliability of the bits based on the first intermediary dataset and the second intermediary dataset.

Abstract: An access point of a wireless communication network forms beams by applying a weightset for a beamforming weights matrix to signal streams. The Equivalent Isotropic Radiated Power (EIRP) that is emitted from an array of antenna elements at the access point is controlled by calibrating the transmission phase and gain of a respective transmit chain for each antenna element, providing a polar radiation model for an antenna element of the array, and determining a weightset for the weighting matrix subject to a constraint that a maximum total EIRP for the beams in combination in any azimuth direction is maintained within a predetermined EIRP limit, based at least on a spatial separation of the antenna elements, the polar radiation model and the calibrated transmission phase and gain of each respective transmit chain.

Abstract: An equalizer includes an equalizer circuit including a signal input to receive a first frequency-domain signal, another signal input to receive a second frequency-domain signal, and an equalized signal output to provide a first equalized signal based upon the first and second frequency-domain signals. Another equalizer circuit includes a signal input to receive a third frequency-domain signal, another signal input to receive a fourth frequency-domain signal, and an equalized signal output to provide a second equalized signal based upon the third and fourth frequency-domain signals. A third equalizer circuit includes a signal input coupled to the equalized signal output of the first equalizer circuit to receive the first equalized signal, another signal input coupled to the equalized signal output of the second equalizer circuit to receive the second equalized signal, and an equalized signal output to provide a third equalized signal based upon the first and second equalized signals.

Abstract: A method, apparatus, computer program, data structure, signal relating to: causing correlation of a digital signal provided by a receiver with a motion-compensated correlation code, wherein the motion-compensated correlation code is a correlation code that has been compensated before correlation using one or more phasors dependent upon an assumed or measured movement of the receiver.

Abstract: A signal frequency conversion circuit is configured to reduce power consumption and resource costs of the signal frequency conversion circuit. Embodiments of the present disclosure include a primary-stage frequency conversion module and at least one subsequent-stage frequency conversion module that is in series connection, where the primary-stage frequency conversion module includes a first filter and a numerically controlled oscillator NCO, and an output of the first filter is connected to an input of the NCO; each subsequent-stage frequency conversion module includes a second filter and a subsequent-stage frequency conversion unit, and an output of the second filter is connected to an input of the subsequent-stage frequency conversion unit; and an output of the NCO is connected to an input of a second filter in a first subsequent-stage frequency conversion module in the at least one subsequent-stage frequency conversion module in series connection.

Abstract: A system for an orthogonal frequency division multiplexed (OFDM) equalizer, said system comprising a program memory, a program sequencer and a processing unit connected to each other, wherein the processing unit comprises an input selection unit, an arithmetic logic unit (ALU), a coprocessor and an output selection unit; further wherein the program sequencer schedules the processing of one or more symbol-carrier pairs input to said OFDM equalizer using multiple threads; retrieves, for each of the one or more symbol-carrier pairs, multiple program instructions from said program memory; generates multiple expanded instructions corresponding to said retrieved multiple program instructions; and further wherein said ALU performs said processing of the one or more symbol-carrier pairs using the multiple threads across multiple pipeline stages, wherein said processing comprises said ALU executing arithmetic operations to process said expanded instructions using said multiple threads across the multiple pipeline stag

Abstract: An embodiment of a receiver includes a first number of antennas and a signal analyzer. The antennas are each spaced from another of the antennas by approximately a distance, and are configured to provide, at one or more wavelengths that are greater than twice the distance, a channel capacity that exceeds a saturation channel capacity. The signal analyzer is configured to recover information from a second number of signals each received by at least one of the antennas over a respective one of a third number of signal pipes, and each having a wavelength that is greater than twice the distance, the second number being related to the third number. Such a receiver can be a multiple-input-multiple-output orthogonal-frequency-division-multiplexing (OFDM-MIMO) receiver that can be configured to increase the information-carrying capacity of a channel (i.e., increase the channel capacity) above and beyond a saturation capacity of the channel.

Abstract: Embodiments disclosed herein include distributed antenna systems (DASs) supporting expanded, programmable communications services distribution to remote communications service sector areas. In one embodiment, the DAS includes a first programmable switch for distributing downlink communications signals into one or more communications service sector sets. The DAS further includes a second programmable switch configured to distribute the one or more communications service sector sets to one or more remote communications service sector areas. A configurable extender module is also included to provide expanded routing of communications service sector sets in the DAS.

Abstract: A communication device includes: a plurality of sensors, each of which includes at least one sensor element that detects information relating to a single detection target and an output circuit that generates an output signal based on a detection signal of the sensor element and transmits the output signal; and a controller that acquires the output signal. One of the sensors transmits the output signal to the controller at an output timing that is shifted, by a predetermined period shorter than a length of one period of the output signal, from another output timing when another one of the sensors transmits the output signal.

Abstract: Methods and apparatus, including computer program products, are provided for receivers. In one aspect there is provided an apparatus. The apparatus may include an in-phase sigma delta receiver coupled to a radio frequency input port providing at least a first carrier aggregation signal and a second carrier aggregation signal; and a quadrature phase sigma delta receiver coupled to the radio frequency input port providing at least the first carrier aggregation signal and the second aggregation signal, wherein the in-phase sigma delta receiver and the quadrature phase sigma delta receiver each include a resonator stage circuitry including at least one variable capacitor that varies notch frequencies to provide passbands for the first carrier aggregation signal and the second carrier aggregation signal. Related apparatus, systems, methods, and articles are also described.

Abstract: Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.

Abstract: A power outlet for controlling power to an external device and transmitting data to the external device, the power outlet including: a housing containing at least one alternating-current power input connection; a power output connection; a data connector; a sensor module; a wireless communication module, including an antenna; a processing unit configured to receive data and control an electrically connected device through the power output connection and/or data connector based on the received data.

Abstract: The present invention relates to the field of signal processing, and discloses code modulation and demodulation methods, apparatuses, and a system, so as to reduce an envelope fluctuation degree of a signal and improve system performance. A specific implementation method includes: receiving, by a sending apparatus, N channels of bit signals, and performing serial-to-parallel conversion on any channel of bit signal of the N channels of bit signals, to generate two channels of first bit signals; performing delay control on the two channels of first bit signals, to generate two channels of code bit signals; performing QAM mapping on the two channels of code bit signals and other N?1 channels of bit signals, to generate a channel of quadrature electrical signal and a channel of in-phase electrical signal; modulating the quadrature electrical signal and the in-phase electrical signal, to obtain a transmit signal.

Abstract: The present disclosure discloses a method for adjusting one or more LO frequencies in a receiver. The receiver performs down conversion on a received signal through one or more mixers by using the one or more LO frequencies, and outputs one or more symbols through an ADC. The method comprising the steps of: for each of the one or more LO frequencies, estimating a new LO frequency corresponding to a best signal quality of the received signal; and adjusting the LO frequency into the new LO frequency. The present disclosure also relates to a receiver for adjusting one or more LO frequencies.

Abstract: A super-regenerative receiver (SRR) circuit includes an amplifier configured to amplify an input injection signal and output the amplified injection signal to an oscillator; and a feed-forwarding unit configured to feed-forward, to the oscillator, a filtered signal obtained by filtering the injection signal after converting a frequency of the injection signal to another frequency; wherein the oscillator is configured to receive an input of a signal in which the filtered signal is applied to the injection signal.

Abstract: The present application discloses various implementations of an antenna configured for use in a wireless transmitter, receiver, or transceiver. In one exemplary implementation, a wireless transmitter includes the antenna configured to be connected to the wireless transmitter. The antenna includes first and second substantially concentric pluralities of antenna elements, the second plurality of antenna elements being rotated with respect to the first plurality of antenna elements. The antenna is configured to enable the wireless transmitter to transmit a communication signal.

Abstract: A method implemented by a transmitter, comprising encoding digital in-phase and quadrature-phase (IQ) data associated with a plurality of analog signals according to a first multi-level modulation format to produce a modulated IQ signal, encoding control information associated with the plurality of analog signals according to a second multi-level modulation format that is different from the first multi-level modulation format to produce a modulated control signal, aggregating the modulated IQ signal and the modulated control signal via time-division multiplexing (TDM) to produce an aggregated TDM signal, and transmitting the aggregated TDM signal over a communication channel.

Abstract: An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.