Abstract: Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where the mandrels are formed of amorphous carbon and the spacer material is silicon oxide, the silicon oxide is first deposited by a plasma enhanced deposition process and then by a thermal chemical vapor deposition process. Oxygen gas and plasma-enhanced tetraethylorthosilicate (TEOS) are used as reactants in the plasma enhanced process, while ozone and TEOS are used as reactants in the thermal chemical vapor deposition process. The oxygen gas is less reactive with the amorphous carbon than ozone, thereby minimizing deformation of the mandrels caused by oxidation of the amorphous carbon.

Abstract: A design structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.

Abstract: A thin film transistor includes: a gate electrode; source and drain electrodes insulated from the gate electrode; an organic semiconductor layer that is insulated from the gate electrode and electrically connected to the source and drain electrodes; an insulating layer that insulates the gate electrode from the source and drain electrodes or the organic semiconductor layer; a hydrophobic layer which covers the source and drain electrodes or insulating layer and has an opening that defines a region corresponding to the organic semiconductor layer; and a hydrophilic layer formed in the opening of the hydrophobic layer, wherein the organic semiconductor layer is formed on the hydrophilic layer. The thin film transistor includes the organic semiconductor layer having a highly precise pattern that is formed without an additional patterning process.

Abstract: An array substrate for a liquid crystal display device comprises a data line, source and drain electrodes disposed on a substrate; a pixel electrode disposed in a pixel region and contacting the drain electrode; an organic semiconductor layer disposed on the substrate; a gate insulating layer disposed on the substrate; a gate electrode disposed on the substrate; a first passivation layer of a photosensitive having a gate contact hole on the gate electrode, the gate contact hole exposing the gate electrode; and a gate line disposed on the first passivation layer, the gate line crossing the data line to define the pixel region and contacting the gate electrode through the gate contact hole, wherein the organic semiconductor layer, the gate insulating layer, and the gate electrode have a substantially same shape.

Abstract: A method for fabricating a structure according to the present invention includes the steps of: forming a groove in a substrate, dropping a solution in which microstructures such as nanowires are dispersed into the groove and the step of evaporating the solution to arrange the microstructures in the groove in a self-organizing manner.

Abstract: A method of manufacturing a non-volatile memory including the following steps is provided. First, a dielectric layer, a first conductive layer and a patterned mask layer are sequentially formed on a substrate. A portion of the first conductive layer is removed using the patterned mask layer as a mask to form a plurality of first gates. An oxidation process is performed to form an oxide layer on the sidewalls of the first gates. The patterned mask layer is removed. A plurality of second gates is formed between two adjacent first gates so that the first gates and the second gates co-exist to form a memory cell column. A doped region is formed in the substrate adjacent to the memory cell column.

Abstract: A semiconductor sensor is contained in a cylindrical housing, an opening of which is closed with a cover member. The cover member includes a mounting plate integrally molded therewith. Components including a bare sensing chip and other circuit chips are directly mounted on a flat surface of the mounting plate. The components mounted on the flat surface are covered with gel having a high flowability. The gel is prevented from flowing out of the flat surface toward the cover member by banks formed at both sides of the flat surface. On an inner wall of the bank, curved surfaces and depressions are formed to surely suppress creeping up of the gel and to trap the gel therein if it creeps up the inner wall of the bank. Thus, the gel is surely prevented from flowing out even though the banks do not entirely surround the flat mounting surface.

Abstract: A power semiconductor module is disclosed, including a plate-type substrate fitted with at least one component, and a base plate provided for dissipating heat from the component via the substrate. In at least one embodiment, a supporting apparatus, which keeps the substrate in thermal contact with the base plate, has a central pressure bolt adjoined by a plurality of stamps which extend in different directions and are intended to contact-connect the substrate, the individual stamps being at non-uniform distances from the substrate in the mechanically unloaded state of the pressure bolt.

Abstract: A base semiconductor component for a semiconductor component stack is disclosed. In one embodiment, the base semiconductor component has a semiconductor chip arranged centrally on a stiff wiring substrate. The wiring substrate has, in its edge regions, contact pads which are electrically connected to external contacts and at the same time to contact areas of the semiconductor chip and also to stack contact areas. The stack contact areas simultaneously form the upper side of the base semiconductor component and have an arrangement pattern corresponding to an arrangement pattern of external contacts of a semiconductor component to be stacked.

Abstract: An anodic metal layer, e.g., a tantalum layer, is deposited. An anodization mask is formed, the anodization mask exposing first portions of the tantalum layer and covering second portion of the tantalum layer. The exposed first portions of the tantalum layer are anodized to form a tantalum pentoxide layer. The amount of the tantalum layer converted to the tantalum pentoxide layer is precisely controlled by the applied anodization potential. Accordingly, the thicknesses of the remaining tantalum layer and the formed tantalum pentoxide layer are precisely controlled allowing the values of passive devices, e.g., resistors and capacitors, formed with the tantalum layer and/or the tantalum pentoxide layer to be precisely set.

Abstract: In an exemplary embodiment, a packaged device having enhanced thermal dissipation characteristics includes a semiconductor chip having a major current carrying or heat generating electrode. The semiconductor chip is oriented so that the major current carrying electrode faces the top of the package or away from the next level of assembly. The packaged device further includes a conductive clip for coupling the major current carrying electrode to a next level of assembly, and a heat spreader device formed on or integral with the conductive clip. A portion of the heat spreader device may be optionally exposed.

Abstract: A structure and a method for preventing latchup. The structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.

Abstract: The present invention provides a method of fabricating a biosensor. The method includes providing a substrate which has a surface coating. The surface coating is deformable and the substrate includes a layered structure which has at least two electrically conductive layers separated by at least one electrically insulating layer. The method also includes imprinting a structure into the surface coating. Further, the method includes etching at least a region of the imprinted structure and the substrate to remove at least a portion of the structure and the substrate. The structure is shaped so that the etching forms at least a portion of the biosensor in the substrate and exposes at least a portion of each electrically conductive layer to form electrodes of the biosensor.

Abstract: A microelectronic device, a method of fabricating the device, and a system including the device. The device includes: a substrate including a polymer build-up layer, and a passive structure embedded in the substrate. The passive structure includes a top conductive layer overlying the polymer build-up layer, a dielectric layer overlying the top conductive layer, and a bottom conductive layer overlying the dielectric layer. The device further includes a conductive via extending through the polymer build-up layer and electrically insulated from the bottom conductive layer, an insulation material insulating the conductive via from the bottom conductive layer, and a bridging interconnect disposed at a side of the top conductive layer facing away from the dielectric layer, the bridging interconnect electrically connecting the conductive via to the top conductive layer.

Abstract: It is an object of the present invention to reduce the consumption of materials for manufacturing a display device, simplify the manufacturing process and the apparatus used for it, and lower the manufacturing costs. The present invention provides a technique to manufacture a display device, applying a means to form a pattern such as a contact hole formed in a semiconductor film, a wiring or an insulating film, or a mask pattern to form such a pattern by drawing directly, a means to remove a film, such as etching and ashing, and a film forming means to selectively form an insulating film, a semiconductor film and a metal film on a predetermined region.

Abstract: This disclosure relates to misalignment-tolerant processes for fabricating multiplexing/demultiplexing architectures. One process enables fabricating a multiplexing/demultiplexing architecture at a tolerance greater than a pitch of conductive structures with which the architecture is capable of communicating. Another process can enable creation of address elements and conductive structures having substantially identical widths.

Abstract: A method for forming an ultra thin die electronic package includes disposing a first polymer film on a first substrate, applying a first adhesive layer to the first polymer film, disposing at least one die on the first adhesive layer, disposing a second polymer film on at least one additional substrate, applying a second adhesive layer to the second polymer film on at least one additional substrate, applying a second adhesive layer to the second polymer film, and attaching the first substrate and the at least one additional substrate via the first adhesive layer and the second adhesive layer such that the at least one die is interspersed between. The method also includes forming multiple vias on a top and/or bottom side of the first and the additional substrate(s), wherein the multiple vias are directly connected to the die, and forming an electrical interconnection between the first substrate, the at least one additional substrate and a die pad of the at least one die.

Abstract: By performing x-ray analysis of stacked metallization layers on the basis of data reduction, the crystalline structure of individual metallization layers may be determined. Consequently, a relationship between electromigration and crystallinity, as well as a correlation between process parameters and materials and the finally obtained crystalline structures of metal lines, may be estimated in a highly efficient manner compared to measurement techniques based on charged particles.

Abstract: A semiconductor device includes a first MIS transistor of a non-salicide structure and a second MIS transistor of a salicide structure which are both formed on a substrate of silicon. The first MIS transistor includes a first gate electrode of silicon, first sidewalls, a first source and drain, and plasma reaction films grown in a plasma atmosphere to cover the top surfaces of the first gate electrode and first source and drain, wherein the plasma reaction film prevents silicide formation on the first MIS transistor.

Abstract: A semiconductor chip manufacturing process includes sticking a protective sheet onto a first surface of a semiconductor wafer so that the sheet comes in contact with the TEG, placing a mask on a second surface that is a surface opposite from the first surface, performing plasma etching on the second surface to remove portions corresponding to dividing regions and separate device-formation-regions into individual semiconductor chips, and removing the TEG in a state where it remains unremoved in the dividing regions and stuck to the protective sheet together with the protective sheet by peeling off the protective sheet.