Abstract: A photocathode. The photocathode includes an absorber. The absorber a p-type bulk active layer and a plurality of nanostructures formed on the p-type bulk active layer. The Photocathode further includes the plurality of nanostructures, such that the plurality of nanostructures are formed at a band bending region between the bulk active layer and the vacuum.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. A substrate is provided. A multi-layer structure is formed over the substrate, wherein the multi-layer structure includes a semiconductive material layer and an oxide layer over the semiconductive material layer. The oxide layer is patterned to form a first patterned layer. A second patterned layer is formed on the semiconductive material layer and alternately arranged with the first patterned layer. A first etching operation is performed on the substrate using a comprehensive pattern of the first patterned layer and the second patterned layer.

Abstract: The disclosure provides an array substrate, a display panel and a method for manufacturing an array substrate. The array substrate includes a substrate having a display area and a peripheral area around the display area; a first electrode provided on the substrate and disposed in the peripheral area; an opening disposed in the first electrode, wherein the opening passes through a surface of the first electrode away from the substrate and reaches a surface of the first electrode toward the substrate; a dielectric layer on the first electrode; and a conductive portion on the dielectric layer, wherein the conductive portion, the dielectric layer and the opening form an antenna.

Abstract: Disclosed is a display device with integrated touch screen comprising a substrate, a first insulating layer provided on the substrate, a second insulating layer provided on the first insulating layer, a dam provided on the second insulating layer, a layer protection part provided outside the dam, and a touch insulating layer provided on the encapsulation layer.

Abstract: A memory device includes a source layer, an alternating stack of insulating layers and electrically conductive layers located over a proximal horizontal surface of the source layer, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, a source-control-gate dielectric located over a distal horizontal surface of the source layer which is opposite to the proximal surface of the source layer, and a source-control electrode located over the source-control-gate dielectric.

Abstract: A semiconductor device includes first and second active patterns respectively provided on a first and second PMOSFET regions of a substrate, a first channel pattern on the first active pattern, the first channel pattern including first semiconductor patterns stacked and spaced apart from each other, a second channel pattern on the second active pattern, the second channel pattern including second semiconductor patterns stacked and spaced apart from each other, a first gate electrode on the first channel pattern, and a second gate electrode on the second channel pattern. A first concentration of aluminum (Al) or silicon (Si) in an inner gate electrode of the first gate electrode is different from a second concentration of aluminum (Al) or silicon (Si) in an inner gate electrode of the second gate electrode.

Abstract: A display apparatus includes a semiconductor layer arranged on a substrate and including a channel area and a source area and a drain area respectively arranged at both sides of the channel area, the semiconductor layer including an opening portion arranged to be adjacent to one of the source area and the drain area, an electrode overlapping in a plan view and electrically connected to one of the source area and the drain area, and an insulating pattern arranged between the semiconductor layer and the electrode, wherein a first edge of the electrode adjacent to the opening portion is spaced apart from the opening portion, and an edge portion of the insulating pattern adjacent to the opening portion is spaced apart from the opening portion.

Abstract: A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate, an upper structure, a vertical transistor an electrical pad. The upper structure is disposed on the substrate and defines a hole. The vertical transistor is disposed in the hole. The electrical pad is disposed in the hole and on the vertical transistor. A top surface of the electrical pad is substantially aligned with a topmost surface of the upper structure.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. A substrate is provided. A multi-layer structure is formed over the substrate, wherein the multi-layer structure includes a semiconductive material layer and an oxide layer over the semiconductive material layer. The oxide layer is patterned to form a first patterned layer. A second patterned layer is formed on the semiconductive material layer and alternately arranged with the first patterned layer. A first etching operation is performed on the substrate using a comprehensive pattern of the first patterned layer and the second patterned layer.