Patents Examined by David A. Zaincke
  • Patent number: 6891253
    Abstract: Arrangements are provided to effectively prevent wire disconnection generated due to an increase of heat applied to a semiconductor integrated circuit device. The semiconductor integrated circuit device is structured such that a metal layer containing a Pd layer is provided in a portion to which a connecting member having a conductivity is connected, and an alloy layer having a melting point higher than that of an Sn—Pb eutectic solder and containing no Pb as a main composing metal is provided outside a portion molded by a resin. Further, a metal layer in which a thickness in a portion to which the connecting member having the conductivity is adhered is equal to or more than 10 ?m is provided in the connecting member.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: May 10, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda