Patents Examined by David A. Zaineke
  • Patent number: 6844490
    Abstract: A superconducting cable having at least one phase and having: a) a layer of tapes of superconducting material; b) a tubular element of superconducting material for supporting said layer of tapes, said tubular element having at least one portion made of metallic material, and being in electrical contact with the layer of tapes of superconducting material; c) a cooling circuit adapted to cool the superconducting material to a working temperature not higher than its critical temperature, having a fluid at a predetermined working pressure ranging between a minimum value and a maximum value; wherein the deformation of said tapes of superconducting material, consequent to a temperature variation between the room temperature and the working temperature of the cable is lower than the critical deformation of the same tapes.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: January 18, 2005
    Assignee: Pirelli Cavi E Sistemi S.p.A.
    Inventors: Marco Nassi, Pierluigi Ladieā€²
  • Patent number: 6790747
    Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of forming a stressed region in a selected manner at a selected depth (20) underneath the surface. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: September 14, 2004
    Assignee: Silicon Genesis Corporation
    Inventors: Francois J. Henley, Nathan W. Cheung
  • Patent number: 6762369
    Abstract: A multilayer ceramic substrate includes a glass ceramic body, a conductive pattern, and a via conductor. The conductive pattern is formed in the glass ceramic body and on at least one principal surface of the glass ceramic body. The via conductor makes a connection between the predetermined conductive patterns. The via conductor includes a conductive material and a Mo compound or a Mo metal. The conductive material includes at least one selected from the group consisting of Ag, Au, Pt and Pd as a main component. The amount of Mo compound or Mo metal is in the range of 0.05 to 10 parts by weight in terms of Mo metal with respect to 100 parts by weight of the conductive material. This multilayer ceramic substrate can achieve sufficient flatness and high dimensional accuracy, while preventing defects that occurs in the vicinity of electrodes after firing.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: July 13, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ryuichi Saito, Hidenori Katsumura, Hiroshi Kagata
  • Patent number: 6700398
    Abstract: A production test machine pre-screens panels of memory modules for shorts and leakage and other D.C. parameters. Memory modules are constructed as part of a panel of 6 or so modules formed on the same substrate. The modules are connected together by links of the substrate. The D.C. tests are performed on memory modules before separation from the panel (de-panelization), while the modules are still connected together by the panel links. Using parallel testing, a whole panel of modules can be D.C. tested at the same time. Failing modules can then be marked or noted, and the good modules separated from the panel links and sent to a more expensive A.C. tester for functional testing. The spacing or pitch of test heads on the D.C. tester can be adjusted for different sizes of panels.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: March 2, 2004
    Assignee: Kingston Technology Company
    Inventors: Ramon S. Co, Tat Leung Lai
  • Patent number: 5913104
    Abstract: A cutting chuck for use with a cutting blade and for holding a semiconductor wafer in place during a dicing process and a die pick for picking the segmented semiconductor wafer from the chuck. The chuck includes a surface for supporting the wafer and several ports in the surface connected to a vacuum source. Preferably, the cutting chuck includes a housing having a base and a wall. A vacuum chamber is provided within the housing and on top of the base. A porous layer is located in housing and above the vacuum chamber. A surface layer is above the porous layer and contains ports connecting the surface supporting the wafer to the vacuum chamber via the porous layer. In a most preferred embodiment, the chuck is removeably attached to the vacuum source via a check valve. The cutting chuck may also include recesses in the surface to prevent impingement on the cutting chuck by a cutting blade during wafer dicing.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: June 15, 1999
    Assignee: Micron Technology, Inc.
    Inventors: John G. Piper, Chris Keith, Donald M. Heideman, Michael A. Villet