Abstract: The carrier (30) comprises a first etch mask (14), a first metal layer (11), an intermediate layer (12), a second metal layer (13) and a second etch mask (17). Both the first and the second etch mask (14, 17) can be provided in one step by means of electrochemical plating. After the first metal layer (11) and the intermediate layer (12) have been patterned through the first etch mask (14), an electric element (20) can be suitably attached to the carrier (30) using conductive means. In this patterning operation, the intermediate layer (12) is etched further so as to create underetching below the first metal layer (11). After the provision of an encapsulation (40), the second metal layer (13) is patterned through the second etch mask (17). In this manner, a solderable device (10) is obtained without a photolithographic step during the assembly process.

Abstract: One end of an inductor is connected to a drain of a P-channel type MOS transistor. A source of source of MOS transistor is connected to an electric power source which supplies a voltage Vdd. The other end of inductor is connected via a dummy capacitor to a ground. Furthermore, a dummy resistor is connected between a drain of MOS transistor and the ground. The dummy resistor has the same resistance as that of a parasitic resistor existing between the inductor and the MOS transistor. Another dummy capacitor is connected between the dummy resistor and the ground. A current measuring device is connected between a source of MOS transistor and the ground. A current measuring device is connected between a source of MOS transistor and the ground. A current measuring device is connected between a source of MOS transistor and the ground. A current measuring device is connected between a source of MOS transistor and the ground.

Abstract: A test system for testing an electronic device is deployable in two basic configurations. In one of the configurations, a load board (62) that receives a unit (60) of the device is directly attached to a test head (16). In the other configuration, the same load board or one having largely the same pattern of test-head signal transmission positions is coupled through an interface apparatus (66) to a test head. A probe system (64) contacts that load board or/and the interface apparatus. The interface apparatus is normally configured to largely prevent test-head vibrations from being transferred to the probe system. Additionally or alternatively, the load board is vacuum attached to the interface apparatus.

Abstract: A fabricating method for a semiconductor package is proposed, in which a chip carrier accommodates at least one semiconductor chip, which is attached with an interface layer formed on a covering module plate consisting of at least one covering plate, while the interface layer is poor in adhesion to the chip and a molding compound used for forming an encapsulant. So that after completing molding, ball implantation and singulation processes, the interface layer, the covering plate and a portion of the encapsulant formed on the covering plate can be easily removed by heating the singulated semiconductor package. This allows the molding compound not to flash on the chip, and prevents the chip from being damaged by stress generated in the molding process.