Abstract: A device adapted to protect integrated circuits from reverse engineering comprising a part looking like a via connecting two metal layers, but in fact attached only to one metal layer and spaced from the other. Having such “trick” via would force a reverse engineer to think there is a connection where there is none. A method for fabricating such device.
Type:
Grant
Filed:
January 24, 2001
Date of Patent:
September 14, 2004
Assignee:
HRL Laboratories, LLC
Inventors:
Lap-Wai Chow, James P. Baukus, William M. Clark, Jr.