Abstract: An integrated circuit chip die (12) is manufactured with sacrificial structures (16) placed at the areas of die that are likely to experience cracks. According to one embodiment of the invention, these sacrificial structures are placed at the corners of the die. The sacrificial structures are constructed with metal lines (22, 24) that resist propagation of cracks into the area of the die containing electronic devices. The metal lines form lattice steps so that the surface of the die will more tightly bond to the molding compound that makes up the die package.

Abstract: A monolithic integrated semiconductor is proposed, in which on the main surface of a monolithically integrated n-p-n transistor or p-n-p transistor, a cover electrode (D1) is mounted for internal voltage limitation, covering only a single junction region between a highly doped zone (5) and the weakly doped substrate (1). An adjacent highly doped zone (4) is not covered by the cover electrode (D1). By connecting the metal cover electrode (D1) to the pickup (12) for a voltage divider (R1, R2), a breakdown voltage can be adjusted that is higher than the sum of the depletion breakdown voltage and the enhancement breakdown voltage.

Abstract: A semiconductor substrate allowing prevention of the breakdown voltage degradation of a gate oxide film and having a prescribed mechanical strength in order to cope with increase in the diameters of wafers corresponding to reduction in the dimensions of semiconductor devices and improvement in productivity, and a Bi-CMOS semiconductor device allowing electrical characteristics to be maintained in any of a bipolar transistor and a field effect transistor are provided. An epitaxial layer is formed on a silicon wafer formed by means of CZ method. A silicon wafer formed by means of FZ method is joined onto the epitaxial layer. An npn bipolar transistor is formed in the epitaxial layer. An n channel MOS transistor and a p channel MOS transistor are formed in the silicon wafer.