Patents Examined by David Bertelson
  • Patent number: 5013939
    Abstract: A plurality of thin-film transistors constituting an array are successively switched on by gate signals. Feed-through correction capacitances are respectively connected between an output terminal of each thin-film transistor switched on by a certain gate signal and a predetermined number of gate lines for supplying subsequent gate signals. A decrease in an output voltage of each thin-film transistor caused by transmission of a fall of the gate signal to the output terminal via a gate-source capacitance is compensated for by a rise of the subsequent gate signal which is transmitted to the output terminal via the feed-through correction capacitance.
    Type: Grant
    Filed: September 11, 1989
    Date of Patent: May 7, 1991
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Yoshihide Satoh
  • Patent number: 4743781
    Abstract: A new dotting circuit for integrated circuit chips which provides line switching, as well as simultaneous true and complementary outputs, while eliminating the need for the standard collector circuit voltage clamp. This circuit is implemented by the collector dotting of two or more input transistors, the collector dotting of their respective reference transistors, the emitter dotting of one input transistor and a reference transistor to a constant current source, the emitter dotting of the other input transistor and the other reference transistor to a different constant current source, and an inhibit circuit for permitting current to flow to only one of the emitter-dotted circuits in accordance with a logic control signal.
    Type: Grant
    Filed: July 3, 1986
    Date of Patent: May 10, 1988
    Assignee: International Business Machines Corporation
    Inventors: Harsaran S. Bhatia, Harry J. Jones, Shashi D. Malaviya
  • Patent number: 4633106
    Abstract: A circuit is described which holds the bootstrap node of a MOS push-pull end stage at a constant potential even if the end stage has to generate an output H-level. A diode/capacitor charge pump circuit supplies the required pulse current only fed to the node in case of the output H-level.
    Type: Grant
    Filed: May 25, 1984
    Date of Patent: December 30, 1986
    Assignee: ITT Industries, Inc.
    Inventors: Reiner Backes, Friedrich Schmidtpott
  • Patent number: 4410858
    Abstract: This disclosed electric circuit substantially eliminates error output which is caused by unbalanced characteristics of a pair of transistors in a current mirror circuit. An input signal is amplified by a differential amplifier. A current mirror circuit is coupled between said differential amplifier and a power supply. Switching means is coupled to said current mirror circuit for cyclically switching input and output points of said mirror circuit.
    Type: Grant
    Filed: June 22, 1981
    Date of Patent: October 18, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Hiromi Kusakabe