Abstract: A method and system for improving the transfer performance of a jukebox containing multiple media, either single-sided or double-sided, which, although independent, act as a single contiguous drive or volume. By caching writes in one embodiment and caching reads and writes in another embodiment, performance increases by preventing unnecessary disc swapping between the drive or drives of the jukebox. In operation, writes to the media currently in the drive are written through to the media and writes to all other media are cached while the cache does not have a predetermined utilization. When the cache has the predetermined utilization, a different media is placed in the drive and any cached or pending writes for the newly inserted media are sent to the newly inserted media and any corresponding cache entries are cleared.

Abstract: The Centralized Management System utilizing a Bus Interface Unit comprises a Computer (4z) installing an address Bus (4a), data Bus (4b), and control Bus (4c), a First-Level Station (4Q1) communicating with the Computer (4z) as the First-Level Station (4Q1) is connected to the buses (4a, 4b, 4c) of the Computer (4z), a plurality of second-level stations (4Q2, 4Q3, . . . , 4QM) communicating with the First-Level Station (4Q1) as the second-level stations (4Q2, 4Q3, . . . , 4QM) are connected to the First-Level Station through a Multipoint Bus (4r). Therefore, the Centralized Management System is capable of communicating the Computer with the First-Level Station through a Dual Port RAM (Random Access Memory), intercommunicating a plurality of Second-Level Stations through a Multipoint Interface and Multipoint Bus, and controlling and managing several thousands of Terminals (for example, Public Telephones).

Abstract: A plurality of read-ahead FIFOs, each with an LRU replacement policy, is provided for enhancing buffer performance. The FIFO contains a plurality of adaptive buffer replacement counters to monitor usage statistics of the FIFOs and to identify one of the FIFOs as a refill candidate buffer in the event of a miss which requires new data to be brought into one of the FIFOs. Each FIFO has a hit detector and a flush detector for comparing the address of a data request from the bus master with the address stored by each buffer for indicating FIFO hit or invalidate operations. Each FIFO also has a buffer selector to provide data from the buffer selected by the hit detector to the bus master if the selected FIFO buffer has not been invalidated by the invalidate address comparator. The buffer selector otherwise transferring the requested data from the memory to the refill candidate buffer and presenting new data from the refill candidate buffer to the bus master.

Abstract: An array controller of a log structured array dynamically defines segments as data is taken from a write buffer and recorded into disk storage units of the log structured array such that a segment includes blocks selected from the various disk storage units at the time of segment definition so as to minimize disk arm travel. Each time a segment from the write buffer must be written to disk, the new disk segment is defined in response to current disk arm position for each disk platter in a disk storage unit. The array controller maintains a segment definition table that indicates the disk storage unit locations corresponding to each segment. In addition, garbage collection of used blocks is performed in response to disk arm idle time such that garbage collection is not performed only when there are too few empty segments. Rather, garbage collection is performed when a disk arm has been idle for a predetermined time. A variety of garbage collection schemes are described.

Abstract: A Central Processing Unit is provided having an instruction processor for determining CPU instruction types. An instruction detector is included in the CPU for detecting whether a determined instruction is a non-cacheable repeat operation instruction. The CPU has an execution unit for executing instruction and for outputting a CPU signal indicating whether data associated with an instruction is cacheable.

Abstract: A x-y RAM array with a reconfigurable bit width is provided. The array contains a RAM cell columns organized into a number of column groups where the number of groups determines the bit width of the memory. The number of columns in each group are configurable thereby configuring the number of groups and thus the bit width of the memory. Multiplexor logic selects a column from each group to be accessed and passgate logic determines how the multiplexor logic is combined and thus determined the column group configuration. Decode logic provides the appropriate select signals to the multiplexor logic for selecting from the configured number of columns in each group.

Abstract: Circuitry for performing hardware assisted XOR operations to generate parity bits for a disk array system. The circuitry includes a controller that acts as an interface between a PCI bus and a DRAM that includes a write-posting cache portion and an XOR buffer portion. The DRAM has a maximum data storage capacity, and the controller is allocated an address space that is twice the maximum storage capacity of the DRAM. The address space is divided into two portions, a normal address range and an XOR address range. A write to the normal address range produces a normal write cycle to the DRAM, while a write to the XOR address range generates a read-modify-write XOR cycle to the DRAM. In the read-modify-write XOR cycles, the read data are XORed with the write data. Selected data are cumulatively XORed to generate new parity information.

Abstract: A video file server includes an integrated cached disk array storage subsystem and a plurality of stream server computers linking the cached disk storage subsystem to the data network for the transfer of video data streams. The video file server further includes a controller server for applying an admission control policy to client requests and assigning stream servers to service the client requests. The stream servers include a real-time scheduler for scheduling isochronous tasks, and supports at least one industry standard network file access protocol and one file access protocol for continuous media file access. The cached disk storage subsystem is responsive to video prefetch commands, and the data specified for a prefetch command for a process are retained in an allocated portion of the cache memory from the time that the cached disk storage subsystem has responded to the prefetch command to the time that the cached disk storage subsystem responds to a fetch command specifying the data for the process.

Abstract: The cache memory is divided into a plurality of slots, each of which is used to store data files that are staged from the storage devices for transmission to the processor or received from the processor for writing on the storage devices. The management of the plurality of slots is accomplished by the use of at least two sets of lists: global lists and local lists. These lists function to respectively manage the entirety of the cache memory and the slots, either on an individual slot basis or on a virtual device basis. These two sets of lists therefore operate on a substantially orthogonal basis, while also operating cooperatively, to efficiently manage the writing of data into and out of the cache memory.