Abstract: A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region).

Abstract: A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.

Abstract: An output circuit that prevents the flow of a leakage current from its output terminal to a power supply is able to accommodate voltage levels higher than the power supply voltage level. The output circuit includes a p-channel MOS transistor connected between the output terminal and a high potential power supply. A first switch circuit is connected between the transistor and the high potential power supply. The first switch circuit selectively connects and disconnects a back-gate of the transistor and the high potential power supply in response to an external signal applied to the output terminal.