Patents Examined by David E. Martinez
  • Patent number: 11016698
    Abstract: A storage system is coupled to another storage system and a higher-level apparatus via a network, and copies write data received from the higher-level apparatus to the other storage system. This storage system is provided with interface units, each provided with a plurality of ports that can be coupled to the network; and a plurality of controllers coupled to a respective one of the interface units. Each controller has a processor unit. When each processor unit receives write data from the higher-level apparatus via a first port coupled to the interface unit that is coupled to the controller to which the processor unit belongs, the processor unit selects, from among the ports of the interface unit coupled to the controller to which the processor unit belongs, a second port for transmitting the write data to the other storage system, and transmits the write data to the other storage system.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: May 25, 2021
    Assignee: HITACHI, LTD.
    Inventors: Kazuki Hongo, Yasuhiko Yamaguchi
  • Patent number: 11017864
    Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). An initial temperature is stored associated with the programming of data to memory cells in the NVM. A current temperature associated with the NVM is subsequently measured. At such time that a difference interval between the initial and current temperatures exceeds a selected threshold, a preemptive parametric adjustment operation is applied to the NVM. The operation may include a read voltage calibration, a read voltage increment adjustment, and/or a forced garbage collection operation. The operation results in a new set of read voltage set points for the data suitable for the current temperature, and is carried out independently of any pending read commands associated with the data. The initial temperature can be measured during the programming of the data, or measured during the most recent read voltage calibration operation.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 25, 2021
    Assignee: Seagate Technology LLC
    Inventors: Kurt Walter Getreuer, Darshana H. Mehta, Antoine Khoueir, Christopher Joseph Curl
  • Patent number: 11016915
    Abstract: A method for sending data, from an upstream device to a downstream device, including sending a piece of data from one among a plurality of virtual channels sharing the same input buffer memory of the downstream device, if this virtual channel uses a number of memory locations of the input buffer memory strictly less than a current ceiling. It further comprises measuring a communication latency between the upstream and downstream devices, and calculating the current ceiling from the measured latency.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: May 25, 2021
    Assignee: BULL SAS
    Inventors: Pierre Axel Lagadec, Saïd Derradji, Dominique Rigal, Laurent Marliac
  • Patent number: 11003581
    Abstract: An arithmetic processing device includes circuitry configured to add an identifier of a request source that generates a prefetch request into the prefetch request, and output, in response to detecting a certain number of cache hits less than a first threshold, each of the cache hits occurring in a first cache memory provided at a lower hierarchical level than a second cache memory by each prefetch request into which a first identifier is added, a notification for suppressing a prefetch request issued for the lower hierarchical level of the first cache memory from a first request source identified by the first identifier.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 11, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Masakazu Tanomoto, Hideki Okawara
  • Patent number: 11003607
    Abstract: A storage and communication apparatus for plugging into a server, includes a circuit board, a bus interface, a Medium Access Control (MAC) processor, one or more storage devices and at least one Central Processing Unit (CPU). The bus interface is configured to connect the apparatus at least to a processor of the server. The MAC is mounted on the circuit board and is configured to connect to a communication network. The storage devices are mounted on the circuit board and are configured to store data. The CPU is mounted on the circuit board and is configured to expose the storage devices both (i) to the processor of the server via the bus interface, and (ii) indirectly to other servers over the communication network.
    Type: Grant
    Filed: April 12, 2020
    Date of Patent: May 11, 2021
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Avraham Ganor, Reuven Badash
  • Patent number: 10990495
    Abstract: Aspects of the present disclosure involve a system and method for performing operations comprising providing to a client device, a messaging application comprising multiple features; accessing a configuration rule that associates a device property rule with a feature; determining at a first point in time, that a property of the client device matches the device property rule associated with the configuration rule; in response to determining that the property of the client device matches the device property rule associated with the configuration rule, enabling the feature on the client device at the first point in time; receiving an updated property of the client device at a second point in time; and in response to determining that the updated property of the client device fails to match the device property rule associated with the configuration rule at the second point in time, disabling the feature on the client device.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: April 27, 2021
    Assignee: Snap Inc.
    Inventors: Michael Ronald Cieslak, Jiayao Yu, Kai Chen, Farnaz Azmoodeh, Michael David Marr, Jun Huang, Zahra Ferdowsi
  • Patent number: 10990550
    Abstract: In some examples, a logic device may be connected to: (i) a ThunderBolt (TBT) output of a CPU that lacks a DisplayPort (DP) input and (ii) a DP output of a GPU. The logic device may determine a presence of a video signal, e.g., either: (1) TBT video from the CPU or (2) DP video from the GPU. The logic device may re-time the video signal to create re-timed video and output the re-timed video using a USB-C port. If the logic device determines that the video signal is DP, then the logic device may select a DisplayPort Alternate Mode of the USB-C port and output the re-timed video signal using four differential pairs of the USB-C port. If the logic device determines that the video signal is TBT, then the logic device may output the re-timed video signal using two differential pairs of the USB-C port.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: April 27, 2021
    Assignee: Dell Products L.P.
    Inventors: Randall E. Juenger, Arnold Thomas Schnell
  • Patent number: 10990306
    Abstract: Applying a rate limit across a plurality of storage systems, including: determining a rate limit for paired storage systems; receiving, by a first storage system, an amount of I/O operations serviced by the second storage system during a previous predetermined period of time; determining whether the amount of I/O operations serviced by the second storage system is less than half of the rate limit for the paired storage systems; if so, setting local a rate limit for a next predetermined period of time for the first storage system to the difference between the rate limit for the paired storage systems and the amount of I/O operations serviced by the second storage system during the previous predetermined period of time; and otherwise, setting a local rate limit for a next predetermined period of time for the first storage system to half of the rate limit for the paired storage systems.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: April 27, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Mudit Aggarwal, Yuval Frandzel
  • Patent number: 10983926
    Abstract: A driver associated with a host peripheral component interconnect (PCI) device may be initiated, the host PCI device to be accessed by an application executed by a guest operating system (OS) of a guest using user space memory of the guest. A host page table switching instruction may be executed using the driver to cause a switch from a first host page table structure to a second host page table structure. The host PCI device may be accessed using the driver via a PCI alias address that is mapped to a host PCI address in the second host page table structure. Application code associated with the application may be prevented from accessing a host memory address in the second host page table structure.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: April 20, 2021
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, Andrea Arcangeli
  • Patent number: 10970074
    Abstract: A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 6, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas Anton Leyrer, William Cronin Wallace, David Alston Lide, Pratheesh Gangadhar Thalakkal K{dot over (o)}ttilaveedu
  • Patent number: 10969969
    Abstract: An approach to identifying problematic data storage devices, such as hard disk drives (HDDs), in a data storage system involves retrieving and evaluating a respective recovery log, such as a media error section of a device status log, from each of multiple HDDs. Based on each recovery log, a value for a Full Recoveries Per Hour (FRPH) metric is determined for each read-write head of each respective HDD. Generally, the FRPH metric characterizes the amount of time a head has spent performing recovery operations. In response to a particular head FRPH reaching a pre-determined threshold value, an in-situ repair can be determined for the HDD in which the head operates. Similarly, in the context of solid-state drives (SSDs), a latency metric is determinable based on time spent waiting on resolving input/output (IO) request collisions, on which an in-situ repair can be based.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 6, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Robert Lester, Timothy Lieber, Austin Striegel, Evan Richardson, Donald Penza
  • Patent number: 10963390
    Abstract: A memory-adaptive processing method for a convolutional neural network includes a feature map counting step, a size relation counting step and a convolution calculating step. The feature map counting step is for counting a plurality of input channels of an input feature map tile and a plurality of output channels of an output feature map tile for a convolutional layer operation of the convolutional neural network. The size relation counting step is for obtaining a cache free space size in a feature map cache and counting a size relation among a total input size, a total output size and the cache free space size of the feature map cache. The convolution calculating step is for performing the convolutional layer operation according to a memory-adaptive processing technique.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: March 30, 2021
    Assignee: NEUCHIPS CORPORATION
    Inventors: Ping Chao, Chao-Yang Kao, Youn-Long Lin
  • Patent number: 10943617
    Abstract: A server box embodiment is disclosed that generally comprises an array of dummy HDDs that share a common set of universal disk drive components in a master components module, or power module. Each dummy HDDs is constructed without expensive onboard chipsets that control the normal functionality of a standard HDD. By sharing expensive chipsets in a master components module (power module) money can be saved in building and selling the dummy HDD server. Embodiments envision a power module possessing the needed chipset functionality that is missing in a dummy HDD. The power module can be made to move from dummy HDD to dummy HDD supplying the necessary chipset in a shared manner when data is being stored or retrieved for client or end-user.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: March 9, 2021
    Assignee: Spectra Logic Corporation
    Inventors: Nicholas Aldo Nespeca, Jon Benson, Stephen P. Neisen, Matt John Ninesling
  • Patent number: 10936248
    Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data; writing the plurality of data into a first physical erasing unit by using a multi-page programming mode; and writing at least one first data of the plurality of data into a second physical erasing unit by using a single-page programming mode; verifying the plurality of data stored in the first physical erasing unit; and if the verification fails, performing a writing operation to a third physical erasing unit by using the multi-page programming mode according to the at least one first data and the plurality of data.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: March 2, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu
  • Patent number: 10925216
    Abstract: A drive and control system for a lawn tractor includes one or more sensors configured to detect an operational parameter of an aspect of the vehicle, and one or more controllers for controlling one or more components of the vehicle and for receiving data output from the one or more sensors. The controller communicates with the one or more sensors and one or more vehicle modules configured to control one or more vehicle components via a CAN Bus network. The controller may be coupled to an IMU mounted on the vehicle for dynamically controlling the vehicle on sloped terrain, for example. The controller may be accessible from a remote device over a wireless network for communicating setup, diagnostic, and performance data to and from the vehicle.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: February 23, 2021
    Assignee: Hydro-Gear Limited Partnership
    Inventors: Alyn G. Brown, K. Mike McCoy, Gregory Barton Moebs, Gregory E. Arends, Damon J. Hoyda, Jesse L. Probst, Joseph Hamilton
  • Patent number: 10929316
    Abstract: Storage-based slow drain detecting and automated resolution is provided herein. A data storage system as described herein can include a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can include a switch query component that obtains a host transfer rate negotiated between a host device and a network switch from a host-connected port of the network switch; a comparison component that compares the host transfer rate to an array transfer rate negotiated between the network switch and a storage array; and a rate limiter component that limits a data transfer from the storage array to the host device to the host transfer rate in response to the host transfer rate being less than the array transfer rate.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: February 23, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Scott Rowlands, Erik P. Smith, Alan Rajapa, Arieh Don
  • Patent number: 10926768
    Abstract: A drive and control system for a lawn tractor includes a CAN-Bus network, a vehicle controller, a pair of hydrostatic or electric transaxles controlled by respective electronic drive controllers, and one or more steering and drive input devices coupled to respective sensor(s) for sensing user steering and drive inputs. The vehicle controller communicates with one or more vehicle sensors and one or more vehicle controllers that control one or more vehicle components via the CAN-Bus network. The vehicle controller processes the user's steering and drive inputs and posts on the CAN-Bus network digital drive signals configured to obtain the desired speed and direction of motion of the lawn tractor. The electronic drive controllers convert the digital drive signals to appropriate signals for driving the hydrostatic transaxles or the electric transaxles, as equipped, based on tunable motion parameters to obtain the desired speed and direction of motion of the lawn tractor.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: February 23, 2021
    Assignee: Hydro-Gear Limited Partnership
    Inventors: Alyn G. Brown, K. Mike McCoy, Gregory Barton Moebs, Gregory E. Arends, Damon J. Hoyda, Jesse L. Probst, Joseph Hamilton, John Tyler Hibbard
  • Patent number: 10919463
    Abstract: A drive and control system for a lawn tractor includes a CAN-Bus network, a vehicle controller, a pair of hydrostatic or electric transaxles controlled by respective electronic drive controllers, and one or more steering and drive input devices coupled to respective sensor(s) for sensing user steering and drive inputs. The vehicle controller communicates with one or more vehicle sensors and one or more vehicle controllers that control one or more vehicle components via the CAN-Bus network. The vehicle controller processes the user's steering and drive inputs and posts on the CAN-Bus network digital drive signals configured to obtain the desired speed and direction of motion of the lawn tractor. The electronic drive controllers convert the digital drive signals to appropriate signals for driving the hydrostatic transaxles or the electric transaxles, as equipped, based on tunable motion parameters to obtain the desired speed and direction of motion of the lawn tractor.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: February 16, 2021
    Assignee: Hydro-Gear Limited Partnership
    Inventors: Alyn G. Brown, K Mike McCoy, Gregory Barton Moebs, Gregory E. Arends, Damon J. Hoyda, Jesse L. Probst, Joseph Hamilton, John Tyler Hibbard
  • Patent number: 10915485
    Abstract: A circuit for asynchronous data transfer includes a slave device having an asynchronous slave clock for transferring data to a master device having a master clock. The slave clock is a non-continuous clock signal. The slave device includes a clock detection circuit, a register bank, a temporary storage register, and a datapath selector. The slave device receives a data transfer command from the master device. The clock detection circuit detects a presence of the slave clock signal and generates a sync signal. To transfer the data to the master device, the datapath selector selects one of the temporary storage register and the register bank based on the sync signal. The slave device ensures seamless data transfer to the master device regardless of the presence or absence of the slave clock signal.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: February 9, 2021
    Assignee: NXP USA, Inc.
    Inventors: Deepika Chandra, Ramesh M. Sangolli
  • Patent number: 10915469
    Abstract: According to some example embodiments according to the present disclosure, a device includes a printed circuit board (PCB); a solid state drive (SSD) connected at a first side of the PCB via at least one SSD connector; at least one field programmable gate array (FPGA) attached to the PCB at a second side of the PCB; and at least one front end connector attached to the PCB at a third side of the PCB, wherein the device is configured to process data stored in the SSD based on a command received via the at least one front end connector.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: February 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sompong Paul Olarig, Fred Worley