Abstract: The present invention provides a method and apparatus for data processing and virtualization. The method and apparatus are configured to receive communications, separate a command communication from a data communication, parallel process the command communication and the data communication, generate at least one virtual command based on the command communication, and generate virtual data according to the at least one virtual command. The apparatus can comprise a parallel virtualization subsystem configured to separate data communications from command communications and to parallel process the command communications and the data communications, to generate virtual commands and to generate virtual data according to a virtual command, and a physical volume driver coupled with the parallel virtualization subsystem, wherein the physical volume driver receives the virtual data and configures the virtual data.

Abstract: Provided is a method, system, and article of manufacture for inbound packet placement in host memory. A first packet for a buffer in memory is received and a descriptor is generated indicating a length of the first packet and a buffer address of the buffer. At least one subsequent packet following the first packet capable of fitting in the buffer with the first packet is received and a descriptor is generated for each received subsequent packet. The first packet and the at least one subsequent packet capable of fitting into the buffer are transferred to the buffer. The descriptors of the first packet and the at least one subsequent packet written to the buffer are added to a descriptor array.

Abstract: Input/output (I/O) communications subadapters, such as subchannels, of an I/O subsystem are dedicated to components, such as I/O devices, of the I/O subsystem. The subadapters provide information about the associated components, in response to the execution of I/O instructions. To enhance I/O connectivity, a plurality of sets of I/O subadapters is provided to an operating system image. This allows programs of the operating system image to access a same component via different sets of I/O communications subadapters. Further, it enables an operating system image to use more than 64 k subchannels.

Abstract: A system and method are provided for setting up a direct memory access for a first processor. The system includes the first processor and a local memory. The local memory is coupled to the first processor. A first direct memory access controller (DMAC) is coupled to the first processor and the local memory. A system memory is in communication with the first DMAC. A second processor is in communication with the first DMAC such that the second processor sets up the first DMAC to handle data transfer between the local memory and the system memory. The second processor is interrupted when the first DMAC finishes handling the data transfer.

Abstract: The present invention provides an SDIO controller, an SDIO wireless communication card, an SDIO wireless communications module, and a method for transmitting write data from an SDIO host device to an SDIO application. Specifically, the SDIO controller is a single-chip semiconductor device connecting an SDIO-compliant SDIO host device with a plurality of applications via an SD bus, wherein the controller includes: (a) an SD interface operably connectable with the SDIO host device to decode commands received from the SDIO host device, and to return a response to the SDIO host device; (b) one or more application interfaces; and (c) a temporary memory operably connected between the SD interface and the one or more application interfaces.

Abstract: A storage control apparatus concatenates a plurality of logical units to construct a large capacity logical unit, wherein logical units extending over a plurality of controllers can be concatenated. The channel adapter sends an I/O request to one controller which charges one logical unit constituting the concatenation logical unit, out of a plurality of controllers when an I/O request is sent from a host to the concatenation logical unit LU linking a plurality of logical units, executes I/O processing in the one controller, then sends the I/O request to another controller which charges another logical unit constituting the concatenation logical unit, and continues I/O processing in the another controller.

Abstract: A method and related apparatus used for controlling a peripheral device to transfer data to a bus. The peripheral device has a bus interface circuit and a controller. The method includes storing data outputted from the controller into a first storage block of the bus interface circuit, utilizing the bus interface circuit to simultaneously control the first storage block to output its stored data to the bus and control a second storage block of the bus interface circuit to store data outputted from the controller, and utilizing the bus interface circuit to control the second storage block to output its stored data to the bus.

Abstract: The present invention enables the configuration of a disk array device to be changed in accordance with its purpose of use. Plural disk drive groups each comprising plural disk drives 81 are disposed in the same disk drive unit. Respective disk drive groups are connected to respectively different HDD control boards 82. Each HDD control board 82 is disposed with a connection circuit 200 and switch circuits 210. A signal is outputted from a management terminal to switch the switch circuits 210, whereby adjacent HDD control boards 82 can be connected and operated. Also, by switching the switch circuits 210, adjacent HDD control boards 82 can be mutually separated and operated independently.

Abstract: An information processing apparatus having a common storage accessible by a host includes: an NIC group connected with a plurality of communication paths connected to the host; an I/O processing unit for executing I/O processing of the common storage in response to an I/O request of the host; a storing unit for holding log information for each data transfer performed from/to the host; and a communication path selection unit for selecting, as a data transfer path, a communication path having actually indicated good I/O processing performance among communication paths used in the past data transfer approximate in a communication condition by referring to the log information held by the storing unit.

Abstract: A network interface for secure multiprotocol data communication includes a doorbell circuit, a processor, memory, and a bridge circuit. The doorbell circuit responds to physical I/O addresses of the host that are mapped by a memory management unit by a registration process. An application program seeking to use a multiprotocol channel must register the virtual address of host memory where data for communication is or will be stored and register the virtual address of a page of I/O addresses. Access to the doorbell functions and to the host memory via the memory management unit are therefore denied when the requesting process identifier does not successfully compare with the process identifier for the process that performed the registrations. A password may be stored in the network interface in association with a multiprotocol channel identifier and stored in association with the virtual to physical map used for communication.

Abstract: Disclosed is a reprogrammable I/O system for a chip or board system that can be reprogrammed to simulate many I/O interfaces in firmware. The reprogrammable I/O system comprises an I/O cluster, an I/O bus, I/O pins, and logic at the I/O pins. The I/O pins are arranged logically in a row and are grouped into pin groups of eight pins. Each pin group also includes a pin state machine (PSM) and a data FIFO coupled together. Each PSM has chain connections to the two neighboring PSM's. Each data FIFO has chain connections to the two neighbor data FIFO's. The reprogrammable I/O system allows firmware to organize the I/O pins into I/O interfaces. The firmware in PSM's and the I/O cluster that control the operations of the I/O pins can be changed (reprogrammed) so that the I/O system can perform other different interfaces.