Abstract: An scalable multi-reader/single-writer lock implementation that eliminates contention for lock data structures that can occur in large symmetric multi-processing (SMP) computer systems. The present invention includes a registry head data structure for each critical resource within the computer system. Linked to each of the registry head data structures are one or more client data structures that represent each client (i.e., process, thread, interrupt handler, and the like) that needs read and/or write access to the critical resource represented by the registry head data structure. Further, five operations—Initialization, Adding a Client, Deleting a Client, Obtaining Read Access, and Obtaining Write Access—are provided in order to achieve the goal of contention elimination.

Abstract: A method and system for distributing messages on a bus bridge interconnect are described. In one embodiment, the interconnect comprises a number of nodes, a bus bridge, and a number of buses. The method and system insure that the messages have been observed by each node. In one embodiment, a message is initiated at an initiating node. The message is forwarded to an adjacent neighbor node. The adjacent neighbor node processes and forwards the message to its adjacent neighbor node. The message is received at the initiating node in its original or modified form. In one embodiment, the message is removed from the interconnect once it is received by the initiating node. In an alternate embodiment, each node generates an appended message by one appending an extended unique identifier (EUI) to the message. Once the appended message is received at the initiating node, the appended message is saved.

Abstract: A system for preventing bus contention in a multifunction integrated circuit under testing. The system is implemented in an integrated circuit adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit. The integrated circuit includes at least one bus for communicatively coupling the multiple functional blocks. At least a first functional block and a second functional block included in the integrated circuit, the first functional block and the second functional block both coupled to the bus and coupled to accept the test inputs. An output enable controller is also included in the integrated circuit. The output enable controller is coupled to the second functional block and is operable to disable at least one output of the second functional block if a corresponding output of the first functional block is activated.

Abstract: A common hardware page walker includes an arbitration logic block that controls data bus access between the arbitration logic block and multiple translation lookaside buffers (TLBs), such as an instruction TLB and a data TLB. The arbitration logic block simplifies the complexity within the hardware page walker and makes multiple-state data transfer possible. Each unit (i.e., the hardware page walker and a data TLB and an instruction TLB) has a unidirectional bus that it always drives, and the arbitration logic block informs the hardware page walker which of the busses is active during any given cycle. Thus, the hardware page walker can receive only one command per cycle, and needs no extra logic to handle multiple bus access requests.

Abstract: The present invention relates generally to a method for improving the throughput of data transfers on a bus. More specifically, data setup and hold times relative to REQ# and ACK# signal edges are adjusted programmatically to provide greater integrity in the transmission of data.

Abstract: A Fully Interconnected System Architecture (FISA) for an improved data processing system. The data processing system topology has a processor chip and external components to the processor chip, such as memory and input/output (I/O) and other processor chips. The processor chip is interconnected to the external components via a point-to-point bus topology controlled by an intra-chip integrated, distributed switch (IDS) controller. The IDS controller provides the chip with the functionality to provide a single bus to each external component and provides an overall total bandwidth greater than traditional topologies while reducing latencies between the processor and the external components. The design of the processor chip with the intra-chip IDS controller provides a pseudo “distributed switch” which may separately access distributed external components, such as memory and I/Os, etc.

Abstract: A serial interface unit having an input shift register adapted to receive a serial input data from a serial data stream, and a destination request module. The input shift register converting the serial input data into a parallel input data. The input shift register in communication with at least two processors and the destination request module. The destination request module in communication with one of the at least two processors in response to an input shift register status signal and a processor designation signal, the selected processor adapted to receive the parallel input data.

Abstract: A system for preventing bus contention in a multifunction integrated circuit during testing. The system is implemented in an integrated circuit adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit. The integrated circuit includes at least one bus for communicatively coupling the multiple functional blocks. At least a first functional block and a second functional block included in the integrated circuit, the first functional block and the second functional block both coupled to the bus and coupled to accept the test inputs. A bus arbiter is also included in the integrated circuit for granting ownership of the bus. The bus arbiter is operable to disable at least one output of the second functional block if a corresponding output of the first functional block is activated by using a bus grant signal generated for the first functional block.

Abstract: In a system having a plurality of CPUs connected to a plurality of corresponding bus bridges which are connected in tandem, one of the plurality of bus bridges is associated with a memory storing boot programs for activating the plurality of CPUs. The CPU connected to the bus bridge associated with the memory gains access to the memory by accessing a predetermined address of the bus bridge. The remaining CPUs gain accesses to the same address as the predetermined address, of the bus bridges to which are connected respective CPUs. The thus accessed bus bridges have accesses to the memory by accessing the same address as the predetermined address, of the other bus bridges adjacent toward the bus bridge associated with the memory.