Abstract: A data processing system includes an instruction decoder for decoding a string of instructions including an arithmetic operation instruction, an arithmetic operation unit controlled by the instruction decoder for executing a designated arithmetic operation for a received data, the arithmetic operation unit outputting not only the result of the designated arithmetic operation, but also a sign information and an overflow/underflow information of the result of the designated arithmetic operation, and a saturation detecting circuit receiving the sign information and the overflow/underflow information for controlling a selector in such a manner that if an overflow has occurred when the sign information indicates the positive, the selector selects a positive maximum value; if an underflow has occurred when the sign information indicates the negative, the selector selects a negative maximum value; and if neither the overflow nor the underflow has occurred, the selector selects the result of arithmetic operation outp

Abstract: Circuit arrangement for calculating matrix operations, such as those which recur frequently in signal processing, specifically in conjunction with neural networks, having a systolic array of multipliers and adders, downstream from which a recursive accumulator is connected. In addition to products, sums and differences of matrices, this circuit arrangement also allows squares, absolute magnitudes of sums and differences and squares of sums and differences of two matrices to be calculated very efficiently. Furthermore, with the aid of the recursive accumulator, it is possible to transpose matrices, to calculate row sums and column sums, and to search for minimum or maximum matrix elements.

Abstract: Amplitude information is derived from a periodic waveform by digitally sampling the periodic waveform, filtering a digital harmonic signal out of the digital sample sequence of the periodic waveform, and computing the root mean square of the digital Mth harmonic signal over a predetermined number of successive samplings of the periodic waveform. The digital sampling is done at a rate such that there will be an integer number of samples "L" over the period of the first harmonic component of the digital sample sequence of the waveform signal. The root mean square value computation is simplified by selecting the sampling window width N and the harmonic M so that there is a predetermined relationship to a critical sampling number L given by the expression, L=(4MN)/(2j+1) where j=0, 1, 2, . . . . As long as this relationship is satisfied, the RMS value can be computed by summing the absolute value of selected digital amplitude values of the selected harmonic component of the digitized signal.

Abstract: A carry propagation circuit of a parallel-type full adder having a plurality of bits. The carry propagation circuit includes: a control unit for controlling a carry propagation; a main path including a plurality of transfer circuits serially connected and provided for each of the plurality of bits, each transferring a carry signal from a lower bit to a higher bit when it is brought to an ON state by the control unit; and at least one bypath arranged to bypass a predetermined number of the transfer circuits and brought to an enable state or a disable state by the control unit. When the control unit brings the bypath to the enable state, it brings to the OFF state a transfer circuit provided immediately in the lower bit side of the main path seen from a terminated point of the bypath and thus propagates only a carry signal propagated via the bypath to the higher bit side.

Abstract: A logic operation circuit includes an exclusive-OR circuit for receiving first and second input signals, a carry output signal selection circuit for selectively generating a sum signal or an inverted signal thereof as a carry output signal in accordance with an output signal from the exclusive-OR circuit, and a carry output signal selection circuit for selectively generating a carry input signal or the first input signal as a sum signal in accordance with the output signal from the exclusive-OR circuit.