Abstract: A vertical bipolar transistor is fabricated in a semiconductor substrate without an epitaxial layer using oxide isolation and ion implantation techniques. Ion implantation energies in the KEV ranges are used to implant selected ions into the substrate to form a collector region and buried collector layer less than 1 micron from the surface of the device, and then to form a base region of opposite conductivity type in the collector layer and an emitter region of the first conductivity type in the base region. Even though ion implantation techniques are used to form all regions, the base and the emitter regions can, if desired, be formed to abut the field oxide used to laterally define the islands of semiconductor material. The field oxide is formed to a thickness of less than 1 micron and typically to a thickness of approximately 0.

Abstract: A method for changing Josephson device parameters, e.g., the critical current of a Josephson junction. The method comprises incorporating doping material into the device, or part of the device, followed by a light anneal. Exemplary dopants include In, Sn, Sb, Te, Bi, Hg, Mg, Li, Cd, Na and Ta, with In, Sn, and Sb being preferred dopants for changing the critical current of a Josephson junction having a Pb-containing counter electrode. The dopant can be incorporated into the device by in-diffusion after deposition onto the surface, by ion implantation, or by any other convenient method. The amount of dopant required is typically small. For example, deposition of a Sn layer of 0.05 nm effective thickness onto the 200 nm thick Pb-Sb(1.5 wt. %) counter electrode of a cross-type Josephson junction, and annealing at 80.degree. C. for about 3 hours, resulted in an increase in the critical current of the junction by a factor of about 2.5.

Abstract: An apparatus for manufacturing thermoelectric devices includes two conductive strip receiving fixtures, a thermoelectric element receiving fixture and a u-shaped member. The conductive strip receiving fixtures act to retain the strips in proper registry during the processing steps of screen printing insulating material, or solder paste thereon as well as during attachment of thermoelectric elements thereto. The element receiving fixture is complemental with either of the strip receiving fixtures to maintain the elements in place during the coupling of the elements to the strips in one of the strip receiving fixtures. The strip receiving fixtures are complemental with the u-shaped member to complete the coupling of the elements to the strips such that the elements are coupled thermally in parallel and electrically in series. The u-shaped member also facilitates the introduction of a ceramic potting compound therebetween.Also disclosed is a method for manufacturing a thermoelectric device.

Abstract: A high optical quality corner is produced on a cleaved crystal which may include a stripe or surface optical waveguide by making a fracture initiation mark along only a portion of the surface intercept of the desired cleavage plane with a first of two major surfaces of the crystal and then tensioning the first major surface of the crystal to fracture the crystal along the desired cleavage plane beginning at the fracture initiation mark. This produces a high optical quality corner along a portion of the intersection of the newly cleaved surface with the major surface of the crystal. This high optical quality corner is located where no fracture initiation mark was made and enables the crystal to be used in as-cleaved form for end-fire coupling between its waveguide and an external waveguide such as an optical fiber.

Abstract: A sheet of brazing alloy foil, a clad sheet of aluminum, a brazed large section structure or a method of vacuum brazing large aluminium structures utilizing a brazing alloy based on aluminium and containing 4.5 to 13.5% silicon, 0.1 to 1.5% strontium and up to 3% magnesium.

Abstract: A photolithographic method for fabricating thin film transistors and thin film transistor arrays in which the contamination vulnerable semiconductor-insulator interfaces are formed in a single vacuum pump-down operation. To minimize step coverage problems, quasi-planar construction is employed to provide a planar substructure for receipt of the deposited thin semiconductor layer.

Abstract: A method is described for the fabrication of charge-coupled devices by the formation of a thin film lamellar metallic eutectic and subsequent selective removal of one of the eutectic phases to form one of the spaced gate arrays of such devices.

Abstract: A process for placing non-continuous Dual Electron Injection Structures (DEIS) between two layers of polysilicon used to form an array of poly devices on an integrated circuit substrate. Separate masks are used to define Poly 1 and Poly 2 devices, respectively. The DEIS structure is disposed above the poly 1 devices. A silicon nitride (Si.sub.3 N.sub.4) layer is used to mask the DEIS structure and prevents it from oxidizing during certain processing steps. A thin layer of poly x is placed between the DEIS structure and the Si.sub.3 N.sub.4. The poly x layer forms a buffer and protects the DEIS during an etching step which removes the Si.sub.3 N.sub.4 layer.

Abstract: After a silicon layer is selectively grown on that part of a silicon substrate surface on which an electrode is to be formed, the silicon layer is reacted with a refractory metal so as to form the electrode made of a metal silicide layer.

Abstract: A MESFET is fabricated using a self-aligned gate process. This process uses a vertical (anisotropic) etch to self-align the gate and source/drain. The vertical etch, in conjunction with a two-level insulator, creates a barrier between the gate and source/drain, so that when metal is deposited and reacted, and any excess removed, the gate is self-aligned with the source/drain, and contacts to the source/drain and gate are well isolated. The alignment obtained by this process is advantageous in that series channel resistance is reduced, and a more compact structure is attained for improvement in packing density.

Abstract: An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends through the recessed dielectric portion and extends further into the monocrystalline silicon body than the recessed portion. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body.

Abstract: An integrated circuit structure having substrate contacts formed as a part of the isolation structure and method for making the same is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends from the side of the recessed dielectric portion opposite to that portion at the surface of said body into the monocrystalline silicon body. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation.

Abstract: A method and device are disclosed which allows an ohmic electrical contact with P-type semiconductor material using metallic foil at low temperature without significant diffusion of the metal into the semiconductor. The contact exhibits opposition to physical separation and has a predetermined electrical resistance.

Abstract: According to the invention, at least one oxidation-preventing layer (2) is provided on the substrate region (1), while on this layer there is provided an oxidizable layer (3). The oxidizable layer (3) is removed above part of the substrate region (1). An edge portion (5) of the oxidizable layer (3) is oxidized. Subsequently, at least the uncovered part of the oxidation-preventing layer (2) is removed selectively and the exposed part of the substrate region is thermally oxidized through part of its thickness, while practically only at the area of the oxidized edge portion (5) the substrate region (1) is exposed and is etched away through at least part of its thickness in order to form a groove (8), the oxidizable layer (3) and the oxidized edge portion (5) being removed completely. The substrate region may be a mono- or polycrystalline silicon layer. The oxidizable layer may consist of for instance polycrystalline silicon and may be coated with a second oxidation-preventing layer (4).

Abstract: There is disclosed an alloy for use in a zinc galvanizing bath comprising zinc, aluminum and a rare earth-containing alloy such as mischmetal. According to the preferred embodiments, the alloy contains from about 85% to about 97% zinc, from about 3% to about 15% aluminum and from about 5 ppm to about 1.0% mischmetal. The alloy may also contain one or more of the elements Fe, Pb, Sb, Mg, Sn, Cu and Si.

Abstract: A process for forming a resistor structure which comprises a polysilicon strip having a resistor region with tungsten leads formed on opposite ends of the strip. A protective oxide is grown on the sides of the silicon strip preventing undercutting of the oxide layer disposed beneath this strip. This prevents formation of the tungsten under the strip or along the sides of the strip which would otherwise place stress on the strip in addition causing other problems.

Abstract: There is disclosed new and improved multiphase thermoelectric alloys and a method for making the same. The alloys are disordered materials having a multiplicity of matrix crystallites separated by generally disordered grain boundaries containing transitional phases and grain boundary regions of various phases including electrically conductive phases having at least one phase having high electrical conductivity.The alloys are formed from a mixture of at least two separately prepared multiple element compounds preferably a first compound Bi.sub.10 Sb.sub.30 Te.sub.60 or Bi.sub.40 Te.sub.48 Se.sub.12 and a second compound Ag.sub.25 Sb.sub.25 Te.sub.50. These compounds while crystalline, have different crystalline structures. They themselves are polycrystalline and do not represent the most stable crystalline structure. The first compound has a rhombohedral crystalline structure and the second compound has a face centered cubic crystalline structure.

Abstract: A ceramic chip carrier having a lead frame thereon with a removable lead frame support which does not bond to the ceramic during the bonding procedure and is later removed. A perforated ground pad is bonded to the substrate simultaneously with the leads of the lead frame and is attached to the lead frame support. The support area is of reduced thickness relative to the rest of the lead frame so that it does not come in contact with the ceramic substrate during the bonding procedure. After firing and bonding of the lead frame to the substrate, the unbonded support rim is removed by pinch cutting, etching or the like.

Abstract: A monolithic microwave integrated circuit including an integral array antenna. The system includes radiating elements, feed network, phasing network, active and/or passive semiconductor devices, digital logic interface circuits and a microcomputer controller simultaneously incorporated on a single substrate by means of a controlled fabrication process sequence.

Abstract: Magnetic gate, including a magnet having a magnetic pole with an at least partly flat surface, a semiconductor chip having an integrated circuit, a mechanically permeable metal piece, and means attaching the semiconductor chip to the magnetically permeable metal piece for minimizing mechanical stresses acting on the chip to eliminate piezo effects and method of production thereof.