Abstract: A program data managing apparatus comprising memories for storing as program data a source code, technique data on a process for making the source code, and intention data on intention to make the source code; a link indicative of the mutual relationship between program data; a display for displaying the relationship between the program data using the link; a link provided to indicate the relationship between a newly developed source code and the original program data from which the new source code derives; and a display for displaying the source code developed stepwise by that link and the related program data.

Abstract: A system for determining the physical location of nodes on a network. The system includes two stations each of which has a clock. Each station uses its clock to determine the arrival times at the station of a packet transmitted over the network from a first node to a second node and of a reply packet sent by the second node to the first node. The arrival times of the packets and the corresponding reply packets are then used to calculate the distance along the network which separates the first and second node. Measurement of packet arrival times for all of the nodes yields the position of all of the nodes on the network.

Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.

Abstract: An image processing apparatus is constructed by providing in parallel a plurality of dyadic look-up tables (10, 20) to which plural items of image data (I1, I2) read out of respective image memories (40, 50) are inputted. The dyadic look-up tables output data corresponding to a prescribed function, and provide this data to an image arithmetic (30) unit, which executes an operation corresponding to the prescribed function.

Abstract: A microprogram load unit comprising a readable and writable microprogram memory within a central processor unit for storing microprogram, a relatively low speed, readable and writable, nonvolatile memory unit, and a readable and writable memory with battery backup. It is determined whether data of the readable and writable memory with backup has been lost or not when power is turned on. If data loss is not present, microprogram is read out of the readable and writable memory with backup and written into the microprogram memory. If data loss is present, microprogram is read out of the nonvolatile memory unit and is written into the microprogram memory.

Abstract: When a data processing instruction is given to a microprocessor, and the code of a data register subject to designation is held in an instruction register, a first logic level is outputted from the instruction code decoder, but when the register subject to designation is the instruction queuing register in which a subsequent instruction code is to be held, a second logic level is outputted from the instruction code decoder. By the operation of logic switching means, when the first logic level is being outputted, the register select code decoder can select the data register designated, while when the second logic level is being outputted, the register select code decoder can select the instruction queuing register designated. Accordingly, this eliminates the necessity of carrying out the designation of a data register or queuing register in the microprogram, thus making it possible to reduce the size of the microprogram used.

Abstract: In a memory area of a data memory in an IC card, data file definition data for defining a data file is stored from one end of the memory area, and a data file is defined from the other end of the memory area. Area definition data for defining an area in a data file is stored from one end of a data file, and an area is defined from the other end of the data file.

Abstract: In a method of, and apparatus for validating character sequences, for example strings of characters generated by keyboards or keypads in telephone systems, computers, and the like, increased speed and reduced memory requirements are achieved by comparing the characters with a database representing valid sequences of characters, the database comprising one or more segments each comprising valid character sequences. A potential range of characters is extrapolated from a character of the input character sequence taking into account possible values of possible succeeding characters. This potential range of sequences is than compared with a database segment. If there is intersection between the potential range and one of the valid character sequences, and there is no succeeding character in the input character sequence, the input character sequence is determined to be valid.

Abstract: A horizontal computer for execution of an instruction loop with a branch. The computer includes parallel processors, a multiconnect unit for storing operands for the processors, and instruction unit for specifying address offsets and operations to be performed by the processors, and an invariant address unit for combining the address offsets with a modifiable pointer to form source and destination addresses in the multiconnect unit. The instruction unit enables different ones of the processors both as a function of whether a branch instruction is to be executed and as a function of which iteration of the loop is being executed. The processors are enabled by processor control circuitry or by selectively providing instructions to the processors so that different operations are performed during different iterations.

Abstract: A computer system has general purpose registers, control registers and access registers for containing information to allow address space capability. A linkage stack uses protected address space to store state information during program call and program return operations. The linkage stack contains information relating to state entries for the saved information and header and trailer entries to point to other linkage stack sections. A control register contains the pointer to the current linkage stack entry and is changed as the program call or return moves through the stack.

Abstract: There is disclosed a facsimile apparatus capable of communication of image information in the error correction mode and in the memory communication mode, the same memory means in common in both modes, thus economizing the memory capacity required in the apparatus. The communication in the error correction mode is controlled according to the available capacity of the memory.

Abstract: A data flow processor which is so constructed that the destination node number in a program memory is stored at a relative address from, for example, a stored address of the present instruction, and a storing address for the next instruction is obtained by adding the relative address of the next instruction to the address of the present instruction. Hence, an amount of data of storing address of instruction to be executed next executed and included in the respective instructions is reduced, whereby an amount of hardware at the program memory is reduced and the memory access time is contracted.

Abstract: A file server system selectively stores and provides access to files across a local network. The system utilizes adaptive request batching, disk pre-allocation, and shadow inode logic to enable data writing operations to be executed at high speed, while conforming to stateless protocol requirements.

Abstract: A system for making procedure calls can be used with a network of computers. An application program on a local node calls a desired library procedure. The library procedure can be available on the local node or a remote node, and the location need not be known by the application. If the library procedure is available on a remote node, a remote router procedure communicates a procedure identifier to the remote node. The procedure is executed, and any results are returned to the locol node, to be returned to the application program.

Abstract: A multiple disk drive array storage device emulates the operation of a single disk drive. The array storage device includes a large buffer memory and a plurality of asynchronously-operating disk drives. A full physical track of data from each of the disk drives within the array is stored within the buffer memory and concatenated to create a large logical track of data. The large buffer memory and asynchronously-operating disk drives results in a data transfer rate that is faster than the standard disk drive architecture.

Abstract: The invention comprises a multi-dimensional array having an inverted, self-pruning binary tree architecture. The array is capable of doing comparative and computational tasks in one clock cycle of computer operation. The computational results of the invention will be free of rounding errors. Both multiplication and division is performed utilizing base ten modulus in a non-sequential operation.

Abstract: A system is provided for managing a storage medium on which management information, data and associated history information are recorded. The system packs and records history information pieces, which have been recorded on a plurality of sectors, on a single physical sector, or the management information is backed up at a predetermined time point, so as to reduce overhead required for reproduction of the history information during reconstruction of the management information and to speed up the reconstruction processing of the management information. Particularly, achievable high-speed processing for reconstruction of the management information during initialization leads to efficient management of an external storage unit of a document filing system or a computer using the management system.

Abstract: A method and apparatus for updating application databases in real time in a distributed transaction processing environment, such as a service control point, without adversely affecting the throughput of transaction processing or losing substantially any conversational transactions that are being processed while updating is occurring. Specifically, two versions, e.g. an old and a new version, of the application databases exist within a memory device, e.g. a shared disk farm. After the start of a "transfer time period", all transactional messages associated with transactions that were initiated after the start of this period are processed using only the new versions of the application databases, while all transactional messages that are associated with transactions that were initiated prior to the start of this period are processed using the old versions thereof.

Abstract: The invention is an alphabetic keyboard arrangement for convenient and fast typing--for instructional, research or data entry purposes--the phonetic data or phonetic transcriptions of Mandarin Chinese in the pinyin romanization. Its distinguishing features are the following: (1) the keys bearing the letters A, I, O and U are so placed that each is usually struck by a different finger; (2) the keys bearing the letters A, I, O, U, N and G, as these letters stand for the most frequently appearing syllabic final speech sounds, are placed in the row of keys on which the typist's fingers usually rest; (3) the keys bearing the letters A, E, I, U and H are so placed that each is usually struck by the index finger or middle finger of either hand; (4) the keys bearing the syllabic tone quality symbols are in the central are of the keyboard.

Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller.