Patents Examined by David L. Clark
  • Patent number: 5261100
    Abstract: A program data managing apparatus comprising memories for storing as program data a source code, technique data on a process for making the source code, and intention data on intention to make the source code; a link indicative of the mutual relationship between program data; a display for displaying the relationship between the program data using the link; a link provided to indicate the relationship between a newly developed source code and the original program data from which the new source code derives; and a display for displaying the source code developed stepwise by that link and the related program data.
    Type: Grant
    Filed: June 8, 1989
    Date of Patent: November 9, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Fujinami, Hirohide Haga
  • Patent number: 5247464
    Abstract: A system for determining the physical location of nodes on a network. The system includes two stations each of which has a clock. Each station uses its clock to determine the arrival times at the station of a packet transmitted over the network from a first node to a second node and of a reply packet sent by the second node to the first node. The arrival times of the packets and the corresponding reply packets are then used to calculate the distance along the network which separates the first and second node. Measurement of packet arrival times for all of the nodes yields the position of all of the nodes on the network.
    Type: Grant
    Filed: May 25, 1989
    Date of Patent: September 21, 1993
    Assignee: Digital Equipment Corporation
    Inventor: Robert A. Curtis
  • Patent number: 5241660
    Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.
    Type: Grant
    Filed: May 17, 1991
    Date of Patent: August 31, 1993
    Assignee: National Semiconductor Corporation
    Inventors: Martin S. Michael, Prashant A. Kanhere, Richard P. Burnley, Franco Iacobelli, Ta-Wei Chien
  • Patent number: 5237687
    Abstract: A microprogram load unit comprising a readable and writable microprogram memory within a central processor unit for storing microprogram, a relatively low speed, readable and writable, nonvolatile memory unit, and a readable and writable memory with battery backup. It is determined whether data of the readable and writable memory with backup has been lost or not when power is turned on. If data loss is not present, microprogram is read out of the readable and writable memory with backup and written into the microprogram memory. If data loss is present, microprogram is read out of the nonvolatile memory unit and is written into the microprogram memory.
    Type: Grant
    Filed: August 22, 1985
    Date of Patent: August 17, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Okamoto, Hiromasa Yamaoka, Kazuhiko Shimoyama
  • Patent number: 5237656
    Abstract: An image processing apparatus is constructed by providing in parallel a plurality of dyadic look-up tables (10, 20) to which plural items of image data (I1, I2) read out of respective image memories (40, 50) are inputted. The dyadic look-up tables output data corresponding to a prescribed function, and provide this data to an image arithmetic (30) unit, which executes an operation corresponding to the prescribed function.
    Type: Grant
    Filed: February 12, 1990
    Date of Patent: August 17, 1993
    Assignee: Fanuc Ltd.
    Inventors: Mitsuo Kurakake, Shouichi Ootsuka, Yutaka Muraoka
  • Patent number: 5233695
    Abstract: When a data processing instruction is given to a microprocessor, and the code of a data register subject to designation is held in an instruction register, a first logic level is outputted from the instruction code decoder, but when the register subject to designation is the instruction queuing register in which a subsequent instruction code is to be held, a second logic level is outputted from the instruction code decoder. By the operation of logic switching means, when the first logic level is being outputted, the register select code decoder can select the data register designated, while when the second logic level is being outputted, the register select code decoder can select the instruction queuing register designated. Accordingly, this eliminates the necessity of carrying out the designation of a data register or queuing register in the microprogram, thus making it possible to reduce the size of the microprogram used.
    Type: Grant
    Filed: July 16, 1990
    Date of Patent: August 3, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akio Miyoshi
  • Patent number: 5226148
    Abstract: In a method of, and apparatus for validating character sequences, for example strings of characters generated by keyboards or keypads in telephone systems, computers, and the like, increased speed and reduced memory requirements are achieved by comparing the characters with a database representing valid sequences of characters, the database comprising one or more segments each comprising valid character sequences. A potential range of characters is extrapolated from a character of the input character sequence taking into account possible values of possible succeeding characters. This potential range of sequences is than compared with a database segment. If there is intersection between the potential range and one of the valid character sequences, and there is no succeeding character in the input character sequence, the input character sequence is determined to be valid.
    Type: Grant
    Filed: December 21, 1989
    Date of Patent: July 6, 1993
    Assignee: Northern Telecom Limited
    Inventor: Timothy J. Littlewood
  • Patent number: 5226128
    Abstract: A horizontal computer for execution of an instruction loop with a branch. The computer includes parallel processors, a multiconnect unit for storing operands for the processors, and instruction unit for specifying address offsets and operations to be performed by the processors, and an invariant address unit for combining the address offsets with a modifiable pointer to form source and destination addresses in the multiconnect unit. The instruction unit enables different ones of the processors both as a function of whether a branch instruction is to be executed and as a function of which iteration of the loop is being executed. The processors are enabled by processor control circuitry or by selectively providing instructions to the processors so that different operations are performed during different iterations.
    Type: Grant
    Filed: March 27, 1991
    Date of Patent: July 6, 1993
    Assignee: Hewlett-Packard Company
    Inventors: Bantwal R. Rau, Ross A. Towle, David W. Yen
  • Patent number: 5226155
    Abstract: In a memory area of a data memory in an IC card, data file definition data for defining a data file is stored from one end of the memory area, and a data file is defined from the other end of the memory area. Area definition data for defining an area in a data file is stored from one end of a data file, and an area is defined from the other end of the data file.
    Type: Grant
    Filed: August 24, 1989
    Date of Patent: July 6, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuo Iijima
  • Patent number: 5220669
    Abstract: A computer system has general purpose registers, control registers and access registers for containing information to allow address space capability. A linkage stack uses protected address space to store state information during program call and program return operations. The linkage stack contains information relating to state entries for the saved information and header and trailer entries to point to other linkage stack sections. A control register contains the pointer to the current linkage stack entry and is changed as the program call or return moves through the stack.
    Type: Grant
    Filed: July 19, 1991
    Date of Patent: June 15, 1993
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Terry L. Borden, Carol E. Clark, Alan G. Ganek, James Lum, Michael G. Mall, Casper A. Scalzi, Richard J. Schmalz
  • Patent number: 5220439
    Abstract: There is disclosed a facsimile apparatus capable of communication of image information in the error correction mode and in the memory communication mode, the same memory means in common in both modes, thus economizing the memory capacity required in the apparatus. The communication in the error correction mode is controlled according to the available capacity of the memory.
    Type: Grant
    Filed: February 26, 1992
    Date of Patent: June 15, 1993
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takehiro Yoshida
  • Patent number: 5218689
    Abstract: A multiple disk drive array storage device emulates the operation of a single disk drive. The array storage device includes a large buffer memory and a plurality of asynchronously-operating disk drives. A full physical track of data from each of the disk drives within the array is stored within the buffer memory and concatenated to create a large logical track of data. The large buffer memory and asynchronously-operating disk drives results in a data transfer rate that is faster than the standard disk drive architecture.
    Type: Grant
    Filed: June 10, 1992
    Date of Patent: June 8, 1993
    Assignee: Cray Research, Inc.
    Inventor: Thomas G. Hotle
  • Patent number: 5218706
    Abstract: A data flow processor which is so constructed that the destination node number in a program memory is stored at a relative address from, for example, a stored address of the present instruction, and a storing address for the next instruction is obtained by adding the relative address of the next instruction to the address of the present instruction. Hence, an amount of data of storing address of instruction to be executed next executed and included in the respective instructions is reduced, whereby an amount of hardware at the program memory is reduced and the memory access time is contracted.
    Type: Grant
    Filed: December 13, 1989
    Date of Patent: June 8, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinji Komori, Hirono Tsubota, Kenji Shima
  • Patent number: 5218699
    Abstract: A system for making procedure calls can be used with a network of computers. An application program on a local node calls a desired library procedure. The library procedure can be available on the local node or a remote node, and the location need not be known by the application. If the library procedure is available on a remote node, a remote router procedure communicates a procedure identifier to the remote node. The procedure is executed, and any results are returned to the locol node, to be returned to the application program.
    Type: Grant
    Filed: June 8, 1992
    Date of Patent: June 8, 1993
    Assignee: International Business Machines Corporation
    Inventors: Richard T. Brandle, Don L. Goodliffe, Donald E. Keith, Randy A. Robinette, Robert C. Sizemore, Garry J. Smithwick, Anthony J. Zappavigna
  • Patent number: 5218695
    Abstract: A file server system selectively stores and provides access to files across a local network. The system utilizes adaptive request batching, disk pre-allocation, and shadow inode logic to enable data writing operations to be executed at high speed, while conforming to stateless protocol requirements.
    Type: Grant
    Filed: February 5, 1990
    Date of Patent: June 8, 1993
    Assignee: Epoch Systems, Inc.
    Inventors: David Noveck, John Wallace
  • Patent number: 5214599
    Abstract: The invention comprises a multi-dimensional array having an inverted, self-pruning binary tree architecture. The array is capable of doing comparative and computational tasks in one clock cycle of computer operation. The computational results of the invention will be free of rounding errors. Both multiplication and division is performed utilizing base ten modulus in a non-sequential operation.
    Type: Grant
    Filed: June 19, 1989
    Date of Patent: May 25, 1993
    Inventor: David M. Magerman
  • Patent number: 5214781
    Abstract: A system is provided for managing a storage medium on which management information, data and associated history information are recorded. The system packs and records history information pieces, which have been recorded on a plurality of sectors, on a single physical sector, or the management information is backed up at a predetermined time point, so as to reduce overhead required for reproduction of the history information during reconstruction of the management information and to speed up the reconstruction processing of the management information. Particularly, achievable high-speed processing for reconstruction of the management information during initialization leads to efficient management of an external storage unit of a document filing system or a computer using the management system.
    Type: Grant
    Filed: October 9, 1991
    Date of Patent: May 25, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadashi Miki, Masayuki Kozuka
  • Patent number: 5212794
    Abstract: The method uses statistical information obtained by running the computer code with test data to determine a new ordering for the code blocks. The new order places code blocks that are often executed after one another close to one another in the computer's memory. The method first generates chains of basic blocks, and then merges the chains. Finally, basic blocks that were not executed by the test data that was used to generate the statistical information are moved to a distant location to allow the blocks that were used to be more closely grouped together.
    Type: Grant
    Filed: June 1, 1990
    Date of Patent: May 18, 1993
    Assignee: Hewlett-Packard Company
    Inventors: Karl W. Pettis, Robert C. Hansen
  • Patent number: 5212789
    Abstract: A method and apparatus for updating application databases in real time in a distributed transaction processing environment, such as a service control point, without adversely affecting the throughput of transaction processing or losing substantially any conversational transactions that are being processed while updating is occurring. Specifically, two versions, e.g. an old and a new version, of the application databases exist within a memory device, e.g. a shared disk farm. After the start of a "transfer time period", all transactional messages associated with transactions that were initiated after the start of this period are processed using only the new versions of the application databases, while all transactional messages that are associated with transactions that were initiated prior to the start of this period are processed using the old versions thereof.
    Type: Grant
    Filed: October 12, 1989
    Date of Patent: May 18, 1993
    Assignee: Bell Communications Research, Inc.
    Inventor: Vito Rago
  • Patent number: 5212788
    Abstract: A distributed database system has a plurality of databases located at distinct nodes, at least one of the databases comprising a timestamping database. Distributed transactions are committed using a two phase protocol. During the first phase, each cohort to the transaction votes to commit or abort the transaction, and also votes an earliest time and a latest time at which the transaction is to be committed. If all the cohorts vote to commit the transaction and the intersection of the voted time ranges is not empty, then the transaction is committed during the second phase of the protocol. A transaction time is selected from the intersection of the voted time ranges and is used to timestamp all updated data that is durably stored when the transaction is committed. Before the first phase of the two phase commit protocol, each transaction read or write locks data at each node for which it needs read or write access.
    Type: Grant
    Filed: May 22, 1990
    Date of Patent: May 18, 1993
    Assignee: Digital Equipment Corporation
    Inventors: David B. Lomet, Philip A. Bernstein, James Johnson, Kenneth Wilner