Abstract: A semiconductor device comprising a pair of first and second opposing conductors and a lamination of a semiconductor layer and an insulating layer held between, and joined together, the first and second conductors, respectively. The average potential of the second conductor joined to the insulating layer relative to the average potential of the first conductor joined to the semiconductor layer is set so as to have such a direction that the supply of carriers from the first conductor to the semiconductor layer is prevented.

Abstract: A structure used to protect a dielectric is disclosed wherein a transistor located nearby the dielectric is connected in series with a conductor overlying the fragile dielectric such that the transistor gate will accumulate charge along with the conductive material over the fragile dielectric. After fabrication and during normal circuit operation, this transistor device remains in an off state, isolating the fragile dielectric node from other circuitry. In an alternate embodiment the protection transistor is a floating gate depletion device, which would always be on until the circuit is activated. At the time the circuit is activated, the device is turned off by trapping electrons on the gate by avalancing a junction associated with it. In a preferred, embodiment, a buried contact is formed after the conductor overlying the dielectric, usually polysilicon, is formed. This buried contact connects the conductor to the discharging transistor.

Abstract: There is provided a complementary field effect transistor which includes an insulating substrate having a gate electrode formed thereon, a substantially intrinsic semiconductor thin film covering the insulating substrate such that the gate electrode is formed through the insulating substrate at one side of the intrinsic semiconductor thin film, an island p-type semiconductor thin film and an island n-type semiconductor thin film formed over the intrinsic semiconductor thin film, a first pair of electrodes formed over the p-type semiconductor thin film opposite the gate electrode, and a second pair of electrodes formed over the n-type semiconductor thin film, also, opposite the gate electrode on a same side of the intrinsic semiconductor thin film as the first pair of electrodes. A first electrode of each of the first and second pairs of electrodes are electrically connected with each other to form the complementary field effect transistor.

Abstract: This invention provides a resin sealed IC regulator, which comprises a first connecting terminal electrically connected to a generator, a second connecting terminal electrically connected to a device other than the generator, a monolithic IC which controls an operation of the generator, mounted on a conductive member, and connected to both the first connecting terminal and the second connecting terminal and a resin molded portion of an electric insulating resin sealing the monolithic IC and at least a portion of the first and second connecting terminals are connected to the monlithic IC.Whereby an IC regulator which can be effectively used with an electrical load can be obtained, and further, an IC regulator having a more reliable control performance and able to be produced at low production cost can be obtained.

Abstract: A stacked MIS device is comprised of a semiconductor substrate of one conductivity type, a first pair of source and drain regions of the other conductivity type formed in the semiconductor substrate in spaced relation from each other to define therebetween a first channel region, a gate electrode disposed on the first channel region through a gate insulating film so as to extend transversely of the first channel region, a semiconductor film of the conductivity type disposed along the gate electrode through another gate insulating film, and a second pair of source and drain regions of the one conductivity type formed in the semiconductor film in spaced relation from each other to define therebetween a second channel region, the length of second channel region being arranged to intersect with that of the first channel region.

Abstract: A IC device includes an underlying layer of a first conductivity type, an overlying layer of the first conductivity type, an isolation layer of a second conductivity type formed between the underlying and overlying layers, and an isolation region of the second conductivity type extending into the overlying layer from a top surface and separating a second portion from a first portion of the overlying layer. The device also includes a channel region formed in the first portion of the overlying layer to form a vertical MOSFET and an auxiliary region formed in the second portion of the overlying layer to form an auxiliary integrated circuit component. A recombination layer of polycrystalline silicon or other material having abundant recombination centers is located under the second portion of the overlying layer.

Abstract: An electrically erasable programmable memory device which is programmable in the manner of an EPROM and erasable in the manner of an EEPROM. A dielectric layer between the control gate and the floating gate is provided having a high dielectric constant. A thin, uniform gate dielectric layer is provided which demonstrates minimal trapping. Finally, an asymmetrical source/drain junction is provided wherein the source includes a shallow portion and a deeper portion, which deeper portion defines the overlap between the source and the floating gate. In the preferred embodiment the dielectric between the control gate and the floating gate comprises tantalum pentoxide, the thin dielectric layer comprises oxynitride, and the deep diffusion portion of the source comprises phosphorous.

Abstract: A process for manufacturing a DMOS transistor in accordance with the present invention includes the steps of forming a layer of gate insulation (12, 14) on an N type substrate (10). A layer of polycrystalline silicon (16) is formed on the gate insulation layer. A first mask (18) is used to define the polycrystalline silicon gate. A layer of silicon dioxide (20) is then formed on the polycrystalline silicon gate. A second photolithographic mask (22) is formed on the wafer. The deep body region is then formed. Thereafer, portions of the gate insulation layer not covered by the polycrystalline silicon gate are removed. The P type body region (26) and N+ source region (28) are then formed having a lateral extent defined by the edge of the polycrystalline silicon gate. A conductive layer 30 l is formed on the wafer and photolithographically patterned. A passivation layer 34 is then formed on the wafer.