Abstract: A method of accessing values stored in a cache used by a processor of a computer system, whereby two read operations may occur simultaneously is disclosed. Memory blocks from a memory device are loaded into respective cache lines of the cache, and address tags associated with the memory blocks are written into two redundant cache directories of the cache. Thereafter, a first memory block can be read from the cache using the first cache directory, while a second memory block is simultaneously read from the cache using the second cache directory. The cache can have a single cache entry array, or two (redundant) cache entry arrays connected respectively to the two cache directories. If an error occurs when examining a particular address tag in one cache directory, then a redundant address tag can be substituted for the particular address tag by examining a corresponding line of the other cache directory.

Abstract: A method and system for reducing power consumption of a non-blocking cache memory within a data processing system is disclosed. In accordance with a method and system of the present disclosure, a detection unit, having several index-matching bits, is associated with the cache memory within the data processing system. A determination is made as to whether or not there is a match in the cache memory, in response to an occurrence of a cache request while the cache memory is performing a linefill operation. In response to a determination that there is not a match for the cache request in the cache memory, another determination is made as to whether or not there is a match for the cache request with a block of information within the ongoing linefill operation.

Abstract: A system and method accelerate access time to multiplexed data streams. Data streams are stored in a storage medium (120), and a link allocation table (LAT) (160), which is stored in the storage medium (120), maps blocks of a data stream to sectors of the storage medium (120). The LAT (160) is organized as a set of linked lists, and each data stream is associated with a different linked list in the LAT (160). Each link in a linked list includes the sector location for a different block of the data steam. Traversing the links of the linked list gives the sector location of each subsequent block of data. Each data stream is also associated with a cache memory (140). For each link of a linked list that is traversed, a cache interface (150) writes into an appropriate cache (140) the sector location information stored in the link.

Abstract: A method and device for writing blocks from a client to a storage device. First and second caches are provided between the client and the storage device. An I/O management process accepts a write request from the client. If the write request is a write-back request, the I/O management process stores the blocks in the first cache, and transferring the blocks from the first cache to the second cache. If, on the other hand, the write request is not a write-back request, a write-through request is performed in which blocks are stored in the first cache, stored in the storage device, but not stored in the second cache. When the blocks are flushed from the first cache to store the blocks on the storage device, the dirty map of the cache header corresponding to the blocks is cleared from the second cache.

Abstract: An external bus master (205) accesses a DRAM (207) using a memory controller (804) internal to a data processor (3) without the use of external multiplexers or any other external circuitry. The need for external multiplexers and even a dedicated integrated circuit pin for providing external control during external master initiated DRAM accesses is removed by the implementation of a circuit and technique for multiplexing row and column addresses of the DRAM internally within the data processor.

Abstract: Minimal random disk write latency is achieved by limiting the number of logical address blocks that can be serviced by a disk to less that the actual number of physically addressable blocks of the system and having a disk controller dynamically map logical data blocks to physical disk blocks in such a fashion that each logical write can take place to any free location, where the free location can be chosen in any track of the current cylinder.

Abstract: A method for storing and transferring wave table audio samples from system memory to a cache unit. The method creates a linked-list of pages in system memory for storing the audio sample. The linked-list is actually a pointer list indicating the locations in system memory where the audio samples are stored. A Digital Signal Processor (DSP) is able to translate the starting address of the pointer list to retrieve a requested audio sample from the system memory. The requested audio sample is then transferred to the cache unit where the DSP is able to retrieve audio samples in a linear fashion at a rate much faster than individually fetching the required portions of the audio sample from the main memory of the system.

Abstract: In accordance with the invention, a computer system is provided with a flash read-only-memory (ROM), a microcontroller and a data port. The microcontroller initially owns the flash ROM. The microcontroller further has a separate ROM upon which it can execute boot-up instructions. After booting up, the microcontroller checks the flash ROM contents, preferably by performing a check-sum of the flash ROM contents. If the checksum of the flash ROM contents matches an expected value, the microcontroller releases ownership of the flash ROM to the computer system so that the computer system boots-up as normal. If the microcontroller determines that the flash ROM has become corrupted, the microcontroller accesses the data port and looks for a flash programming protocol. If the protocol is present at the data port, the microcontroller receives the data from the data port and programs the flash ROM accordingly.

Abstract: An IC card memory includes a header region for storing information about the IC card memory and information about a format, a chapter attribute table (CAT) region for storing information relating to a single chapter, a cluster index table (CIT) region for storing an address of a single cluster index corresponding to a recorded data block, and a data region for storing digital voice data.