Abstract: A binary operator comprises a plurality of carry select adder circuits each including a cumulative carry propagate signal generating means and a cumulative carry generate signal generating means and/or a plurality of block look ahead carry generator circuits each including a cumulative block carry propagate signal and cumulative block carry generate signal generating means and a real carry signal generating means. The carry select adder circuit does not simultaneously generate two presumed sum signals and select and output one of the presumed sum signals, but directly performs operations on a carry propagate signal, a cumulative carry propagate signal and a cumulative carry generate signal which are necessary for generating the presumed sum signal pair and a real carry signal to calculate the real sum signal.