Patents Examined by David M. Ostrowski
  • Patent number: 5089876
    Abstract: A semiconductor IC device includes a semiconductor pellet, an insulating film, a conductive plate, and a lead frame. A plurality of electrodes and a plurality of active elements are formed on the semiconductor pellet. The insulating film is bonded to a surface of the semiconductor pellet on which the active elements are formed. The conductive plate is arranged on the insulating film. The lead frame includes a plurality of connecting terminals selectively arranged in predetermined regions on the conductive plate through another insulating film, and leads laterally extending from the connecting terminals.
    Type: Grant
    Filed: July 19, 1990
    Date of Patent: February 18, 1992
    Assignee: NEC Corporation
    Inventor: Hiroshi Ishioka
  • Patent number: 5005070
    Abstract: A method and apparatus for attaching the outer leads of a semiconductor package (preferably a Tape Automated Bonded circuit) to the traces on a printed circuit board is described. The outer leads of the package are configured in an angled orientation so that the tip of each lead extends downwardly below the lower surface of the package. As a result, placement of the package against the circuit board causes the leads to be biased downwardly against the traces. In order to accomplish this, the package is secured to the board using a rigid frame structure. The frame structure urges the edges of the package against the board. This insures that the leads make electrical contact with the traces in a fast and efficient manner, while avoiding problems associated with a lack of lead coplanarity.
    Type: Grant
    Filed: December 19, 1988
    Date of Patent: April 2, 1991
    Assignee: Hewlett-Packard Company
    Inventors: John M. Altendorf, Marvin G. Wong
  • Patent number: 4967244
    Abstract: In a power semiconductor component with switch-off facility in which the switch-off capability is achieved by MCT unit cells, IGBT unit cells which are connected in parallel with the MCT unit cells are provided for switching on.This structure ensures an improved switch-on capability and an increased flexibility in designing the component.
    Type: Grant
    Filed: April 7, 1989
    Date of Patent: October 30, 1990
    Assignee: Asea Brown Boveri Ltd
    Inventor: Friedheim Bauer
  • Patent number: 4967259
    Abstract: A conductive layer is formed at the step portion in a dicing line formed vertically and horizontally on a wafer and at a step portion of the region on which a test element for processing control formed inside of the dicing line or an alignment mark are formed, so as to completely cover the step portions. Since the conductive layer does not come off the step portions in subsequent steps, a short circuit of a wiring layer formed on a semiconductor chip region is prevented.
    Type: Grant
    Filed: July 27, 1989
    Date of Patent: October 30, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroshi Takagi
  • Patent number: 4963950
    Abstract: A depletion mode thyristor includes a plurality of regenerative segments and a plurality of non-regenerative segments, each of which is elongated in a first direction. Regenerative and non-regenerative segments are interleaved in a second direction perpendicular to said first direction. A plurality of regenerative segments may be disposed between adjacent non-regenerative segments. Adjacent regenerative or non-regenerative segments are spaced apart by gate electrode segments which are effective, upon application of an appropriate bias voltage, for pinching off the regenerative segments to force the current therein to transfer to the non-regenerative segments to turn the device off. This structure enables large quantities of current to be transferred from regenerative segments to non-regenerative segments during turn-off without inducing detrimental current crowding.
    Type: Grant
    Filed: May 2, 1988
    Date of Patent: October 16, 1990
    Assignee: General Electric Company
    Inventors: Hsueh-Rong Chang, Bantval J. Baliga
  • Patent number: 4954878
    Abstract: An IC chip assembly includes a chip having an array of exposed contacts at a first face thereof, a substrate having an array of exposed contacts at a face thereof and a compliant interposer with exposed contacts at opposite faces thereof positioned between the chip and substrate so that contacts on the opposite faces of the interposer engage the contacts on said chip and substrate, respectively. A thermal transfer member contacts the opposite face of the chip and is engaged to the substrate so as to compress the interposer thereby simultaneously establishing relatively low inductance electrical connections between the chip contacts and the substrate contacts and good thermal contact between the chip and the thermal transfer member. The assembly is particularly adapted to provide power to the chip of a TAB-type integrated circuit assembly which includes a flexible lead frame connected between the chip and the substrate.
    Type: Grant
    Filed: June 29, 1989
    Date of Patent: September 4, 1990
    Assignee: Digital Equipment Corp.
    Inventors: Leslie R. Fox, Paul C. Wade, William L. Schmidt
  • Patent number: 4949164
    Abstract: High heat generation member of electronic integrated circuit etc. is boiled and cooled. A refrigerant steam is generated by cooling of the heat generation member and is condensed by a condenser which is provided an upper portion. A refrigerant steam flow path and a condensed refrigerant flow path from the condenser are separated with a partition wall. The condensed liquid sent back to the partition wall is supplied to the heat generation member through the partition wall.
    Type: Grant
    Filed: July 7, 1988
    Date of Patent: August 14, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Shigeo Ohashi, Heikichi Kuwabara, Tadakatsu Nakajima, Wataru Nakayama, Motohiro Sato, Kenichi Kasai
  • Patent number: 4949158
    Abstract: A semiconductor device provided with a film having an opening and first and second surfaces; a semiconductor chip having first and second surfaces corresponding to the first and second surfaces of the film and positioned inside the opening along the film; a plurality of first leads fixed to the first surface of the film, a tip of each first lead being electrically connected to a first electrode provided on the first surface of the semiconductor chip; at least one second lead fixed to the first surface of the film; an electroconductive member in the form of, e.g., a film, fixed to the second surface of the film and electrically connected to a second electrode provided on the second surface of the semiconductor chip; and a connection member passing through the film and electrically connecting the second lead and the electroconductive member to each other.
    Type: Grant
    Filed: July 12, 1988
    Date of Patent: August 14, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tetsuya Ueda
  • Patent number: 4939570
    Abstract: A TAB package is described which includes a flexible dielectric film with an outer edge, back and front faces and an aperture therein. The front face, as is conventional, is provided with a plurality of beam leads, which leads extend into the aperture and connect to a semiconductor chip. Thermally conductive body means is provided which has a well formed therein, the well defined by a lip comprising the outer rim of the body means. The back face of the semiconductor chip is thermally connected to the thermally conductive body means and the flexible dielectric film is formed to conform to the surface of the well and to extend over its rim whereby the beam leads also conform to the well and rim structure. The beam leads are thereby made available for electrical connection in the vicinity of the rim. Means are also provided for attaching the outer edge of the film to the thermally conductive body means so as to enable flexure of the film in the event of differential expansion or contraction at connection points.
    Type: Grant
    Filed: July 25, 1988
    Date of Patent: July 3, 1990
    Assignee: International Business Machines, Corp.
    Inventors: Harry R. Bickford, Lawrence S. Mok, Michael J. Palmer
  • Patent number: 4939569
    Abstract: Ultraviolet transmitting glasses exhibiting coefficients of thermal expansion between 46-52.times.10.sup.-7 /.degree.C. and transmittances at a thickness of 1 mm of at least 80% at a wavelength of 254 nm which are essentially free of fluoride and consist essentially, in mole percent, of 60-70% SiO.sub.2, 16-20% B.sub.2 O.sub.3, 1-8% Al.sub.2 O.sub.3, 1-6% Li.sub.2 O, 2.5-5% N.sub.2 O, 0-3% K.sub.2 O, and 0-1.25% Cl, w9herein the mole ratio R.sub.2 O:R.sub.2 O.sub.3 is greater than 0.3, but less than 0.5.
    Type: Grant
    Filed: December 11, 1989
    Date of Patent: July 3, 1990
    Assignee: Corning Incorporated
    Inventor: Gerald J. Fine
  • Patent number: 4937653
    Abstract: Integrated circuit chip-to-chip interconnections are made via gold pads on each chip that are bonded to corresponding gold pads on a silicon wafer chip carrier. The pads on the chips and/or the pads on the carrier are characterized by texturing (roughening) with a feature size of the order of a micrometer or less, so that each of the pads on the chip can be attached to each of the pads on the carrier by compression bonding at room temperature--i.e., cold-well bonding. In particular, the texturing of the gold pads on the silicon carrier is obtained by etching V-grooves locally on the surface of the underlying silicon carrier in the regions of the pads, thermally growing a silicon dioxide layer on the silicon carrier, and depositing the gold on the silicon dioxide layer.
    Type: Grant
    Filed: July 21, 1988
    Date of Patent: June 26, 1990
    Assignee: American Telephone and Telegraph Company
    Inventors: Greg E. Blonder, Theodore A. Fulton
  • Patent number: 4918512
    Abstract: A semiconductor package having a unique die cavity configuration wherein each side of the die cavity is arced outward from the center of the die cavity. This configuration is especially well suited for use in laminated multilayer ceramic packages.
    Type: Grant
    Filed: December 19, 1988
    Date of Patent: April 17, 1990
    Assignee: Motorola, Inc.
    Inventor: Norman L. Owens