Abstract: A method for forming a semiconductor on insulator device is provided that begins with an outer semiconductor layer (16). Trenches (12) of a predetermined depth are formed in outer semiconductor layer (16). An insulator layer (20) is formed outwardly from outer semiconductor layer (16). A mesa (18a) having a predetermined thickness is formed by removing portions of outer semiconductor layer (16) to expose a working surface such that mesa (18a) has a thickness substantially equal to the predetermined depth of the trenches (12) after the working surface is exposed.

Abstract: A semiconductor MOSFET device manufactured by a process starting with a doped semiconductor substrate with a P-well and an N-well and field oxide structures on the surface of the P-well and the N-well separating the surfaces of the P-well and the N-well into separate regions and a silicon dioxide film on the remainder of the surface of the P-well and the N-well comprising the steps as follows: forming a mask over the N-well and an under sized mask over one of the separate regions of the P-well performing a field ion implantation of V.sub.t ' ions into the P-well, removing the mask over the portion of the P-well, performing a blanket ion implantation of V.sub.t1 ions over the entire device.

Abstract: In a MOS type semiconductor device, a source region, a channel region and a drain region of a MOS type device are arranged on the same plane, while a gate electrode is also arranged on the same plane adjacent to the channel region. Another set of a source region, a channel region and a drain region may also be arranged on the same plane and the latter MOS device is arranged to the gate electrode. This type of device may be constructed as a CMOS type device.In another type of semiconductor device, the above-mentioned type plane arrangement of the source, channel and drain regions are layered via an insulator layer, while a gate electrode is provided vertically so as to be adjacent to the two channel regions.

Abstract: A set of three-dimensional structures and devices may be wired together to perform a wide variety of circuit functions such as SRAMs, DRAMs, ROMs and PLAs. Both N-Channel and P-Channel transistors can be made. The P-channel devices are fabricated conventionally in separate N-wells or, alteratively, they are constructed in a like manner to the array N-channel devices. N and P diffused wire can be electrically joined at polysilicon contacts.

Abstract: Threshold optimization for SOI transistors is achieved through the formation of a layer of positive charge within the gate to correspond to the positive polarity formed in the substrate by ion implantation for threshold voltage control. A positive charge layer is formed by furnishing sulfur ions on the substrate before growth of an oxide to form a portion of the gate oxide. The sulfur will form a charge layer on the surface of the oxide, and an additional oxide is then deposited on the same to form the gate oxide as a sandwich with the positive charge layer in the same.

Abstract: A field effect transistor is fabricated with a window pad layer that is patterned using a patterned dielectric with sublithographic spacing as an etch mask. Desirable attributes of the transistor include small junction capacitance.

Abstract: A vertical double diffused metal-on-semiconductor device is produced by a method involving the formation of horizontally separated bodies of heavily doped Si and sources by a self-aligned process and a lift-off process along with the formation of trenches having negatively-sloped side-walls.

Abstract: A method for fabricating a junction terminal extension structure for a high-voltage integrated circuit device. The method provides for the formation of two silicon oxide layers having a two-stage shaped final field region oxide in the proximity of the anode of a high-voltage integrated circuit device. A field region anode flat plate can be formed in the area of the two-stage shaped structure. The distance between the edge of the field region flat plate and the surface of the silicon substrate thus be increased to compared to prior art structures, and the electric field intensity therebetween can therefore be reduced, resulting in the increased breakdown voltage to increase the reliability of the integrated circuit device.

Abstract: The described embodiments of the present invention provide a method and structure for actively controlling the voltage applied to the channel of field effect transistors. In the described embodiments, a transistor connected to the channel region is fabricated. The channel transistor has opposite conductivity type to the transistor using the main channel region. The source of the channel transistor is connected to the channel and the drain of the channel transistor is connected to a reference voltage. The same gate is used to control the channel transistor and the main transistor. When a voltage which causes the main transistor to be on is applied, the channel transistor is off, thus allowing the channel to float and allowing higher drive current. On the other hand, when a voltage to turn off the main transistor is applied, the channel transistor is turned on, thus clamping the channel region to the reference voltage. This allows for consistent threshold voltage control of the main transistor.

Abstract: A self-aligned MOSFET incorporating a punchthrough implant, and the method for forming such a transistor. A dielectric layer is used as a hard mask over a semiconductor substrate. A portion of the dielectric layer is removed to expose a region of the semiconductor substrate. A punchthrough implant is made with the remaining portion of the dielectric layer acting as a mask layer such that the doping concentration is raised by the punchthrough implant only in the exposed region of the semiconductor substrate. A doped layer of polysilicon is formed over the region into which the implant was made to provide a self-aligned gate over the highly doped region. A source and drain are formed on opposite sides of the doped region. A protective layer is formed over the device and metallized contacts are formed to the source, drain, and gate.

Abstract: A method for manufacturing a semiconductor integrated circuit device is described. The method comprises forming a plurality of macrocells each comprising a semiconductor integrated circuit on a semiconductor layer of an SOI (silicon on insulator) substrate, subjecting an insulating film for element separation and an insulating film in the substrate to wet etching thereby removing an unnecessary macrocell, and attaching a desired macrocell separated fabricated to the removed macrocell region. The semiconductor integrated circuit device is also described, which is free of defects and has multifunction and high reliability.

Abstract: A method of forming semiconductor devices comprising the steps of forming, by restriction in the increased number of steps by a process close to the normal process, a field effect transistor having a local shallow source/drain diffusion layer on both the sides of a gate electrode for self-matching operation and without etching damages, wherein impurities are ion-implanted onto the semiconductor side wall and onto the substrate surface of both the sides, and thermal treatment operation is effected so as to form the local shallow source/drain diffusing layers by the diffusion for activating the impurities of the deep shallow source drain diffusing layers, thereby to render to be capable of restraining a short channel effect and reducing the parasitic resistance of the semiconductor devices.

Abstract: A projection is formed in a substrate by anisotropic etching and a transistor is contained in the projection. The central portion of the projection covered with a gate electrode is formed as a channel region, and drain and source regions are formed on both sides of the projection by oblique ion implantation with the gate electrode as a mask. Formed below the drain, source, and channel regions is an element isolation section having the composition of the substrate intact. This eliminates the need for an oxide insulating layer below the transistor for easy manufacturing. Carriers generated in the channel region by ionization by collision can also be discharged to the substrate.

Abstract: Method of fabricating a vertical Metal Oxide Semiconductor Heterojunction Field Effect Transistor (MOSHFET) which is in a layered wafer made by successively growing an N.sup.+ silicon layer, and a N.sup.- silicon layer, a P.sup.- Si.sub.1-x Gex layer, a P.sup.- Silicon layer and then, an N.sup.- silicon layer, one on top of the other. Trenches are etched through the top 3 layers to form islands that are the MOSHFETs heterojunction channel. A gate deposited or grown in a trench extends vertically from the drain at the bottom of the trench to the source in the layer near the top of the trench.

Abstract: A method of manufacturing a semiconductor device having a field effect transistor and a device manufactured by this method in which a high packing density can be realized. The field effect transistor includes a gate electrode (31,41) which is separated from a channel region by a first insulating layer (8) and is entirely surrounded by insulating material. For this purpose, a conductive layer (9) which is to form a gate electrode (31,41) is covered with a second insulating layer (10) and both layers are subsequently given the same pattern at least at the area of the channel region. As a result, the gate electrode (31,41) is covered at the upper side with a portion of the second insulating layer (10). The gate electrode (31,41) is laterally insulated by the provision of a third insulating layer (13) which is subsequently etched back anisotropically, whereby a portion (14) thereof remains intact afterwards alongside the side wall of the gate electrode (31,41).

Abstract: The invention provides a method of fabricating a semiconductor device by forming, on a P-type silicon substrate, a memory cell portion partitioned with a field oxide film, forming trenches in self-alignment with a polycrystalline silicon film which act as gate electrodes in the semiconductor device, completely burying second and third oxide films in the trenches, removing the third oxide film near the end of the field oxide film by using a second resist film as a mask and thereafter etching-back the whole surface to cause the second and third oxide films to remain only in the trenches. According to the method, the oxide film can be stably buried in the trenches.

Abstract: The structure and method of this invention provide, for example, electrical isolation between active elements in adjacent rows and/or columns of an integrated circuit by use of a self-aligned field-plate conductor formed over and insulated from the substrate regions that are bounded by the channel regions of field-effect transistors in adjacent rows and that are bounded by the bitlines forming those transistors in a column. The field-plate conductor is formed, for example, in a strip that extends over the isolation areas and thermal insulator regions between row lines of the memory cell array. The field-plate conductor strip is connected to a voltage supply that has a potential with respect to the potential of the semiconductor substrate which causes the isolation areas to be nonconductive. Component density may be increased over that of prior-art structures and methods.

Abstract: The present invention relates to a MESFET in which source and drain regions with inverse slopes are formed on a semi-insulating semiconductor substarate having the insulating layer by using the growth property according to the crystal direction and a channel is electrically separated from the substrate by forming the channel layer and a self-aligned gate electrode sequentially on the top of the void formed by the inverse slopes of the source and drain regions. Thus, the present invention achieves the suppression of the leakage current and the backgating effect without the formation of a buffer layer, the formation of the gate electrode without misalignment, a short effective gate length and a low gate resistivity, thereby operating at high speed.

Abstract: A silicon carbide field effect transfer of the present invention includes a base and source region each formed by a series of amorphizing, implanting and recrystallizing steps. Moreover, the drain, base and source regions extend to a face of a monocrystalline silicon carbide substrate and the source and base regions comprise substantially monocrystalline silicon carbide formed from recrystallized amorphous silicon carbide. The source and base regions also have vertical sidewalls defining the p-n junction between the source/base and base/drain regions, respectively. The vertical orientation of the sidewalls arises from the respective implantation of electrically inactive ions into the substrate during the amorphizing steps for forming the base region in the drain and for forming the source region in the base region. The electrically inactive ions are selected from the group consisting of silicon, hydrogen, neon, helium, carbon and argon.

Abstract: Bidirectional field emission devices (FEDs) and associated fabrication methods are described. A basic device includes a first unitary field emission structure and an adjacently positioned, second unitary field emission structure. The first unitary structure has a first cathode portion and a first anode portion, while the second unitary structure has a second cathode portion and a second anode portion. The structures are positioned such that the first cathode portion opposes the second anode portion so that electrons may flow by field emission thereto and the second cathode portion opposes the first anode portion, again so that electrons may flow by field emission thereto. A control mechanism defines whether the device is active, while biasing voltages applied to the first and second unitary structures define the direction of current flow. Multiple applications exist for such a bidirectional FED. For example, an FED DRAM cell is discussed, as are methods for fabricating the various devices.