Abstract: A frequency doubler includes a multiplexer, a digitally controlled delay circuit, a divide-by-two circuit, a duty cycle detector, and a controller. The multiplexer receives a first clock and output a second clock in accordance with a third clock, in which the first clock has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase. The digitally controlled delay circuit receives the second clock and outputs a fourth clock in accordance with a digital word. The divide-by-two circuit receives the fourth clock and outputs the third clock. The duty cycle detector receives the second clock and outputs a logical signal in accordance with a comparison of a duty cycle of the second clock with a target duty cycle value. The controller outputs the digital word in accordance with the logical signal.

Abstract: In accordance with an embodiment, a method of driving a switching transistor includes receiving an activation signal for the switching transistor and generating a sequence of random values. Upon receipt of the activation signal, a control node of the switching transistor is driven with a drive strength based on a random value of the sequence of random values.

Abstract: A current sense circuit for a pass transistor is described. The circuit comprises a sense transistor having input and control ports that are coupled to input and control ports respectively of the pass transistor. The circuit comprises a differential amplifier comprising a differential input and output. An output port of the pass transistor is coupled to a first port of the differential input and an output port of the sense transistor is coupled to a second port of the differential input. The differential amplifier comprises a first sub-amplifier and a second sub-amplifier that are arranged in parallel and which are operated in an auto-zero phase and in an amplification phase in an alternating manner, and which are operated in the auto-zero phase in a mutually exclusive manner. The output of the differential amplifier is used to control voltage drops across the sense transistor and the pass transistor.

Abstract: A frequency converter comprising a frequency transposition block for samples (11Q_1, 11Q_2), a filtering block (12Q_1, 12Q_2), the filtered samples y(n) verifying y(n)=c(0)·x(n)+c(1)·x(n?1)+c(2)·x(n?2)+ . . . +c(p?1)·x(n?p+1)+c(p)·x(n?p)+c(p?1)·x(n?p?1)+ . . . + . . . +c(1)·x(n?2·p+1)+c(0)·x(n?2·p), wherein x( ) are the transposed samples and c(0), . . . c(p) are the real coefficients of the filter; and being adapted for, during a cycle for determining the value of the filtered sample y(n): calculating the first terms c(0)·x(n), c(1)·x(n?1), c(2)·x(n?2), . . . , c(p)·x(n?p) by multiplying the respective coefficients and transposed samples, and storing in memory said first calculated terms; reading the second terms c(p?1)·x(n?p?1), . . . , c(1)·x(n?2·p+1), c(0)·x(n?2·p), calculated and stored in memory during previous cycles for determining the value of filtered samples y(n?m); and determining y(n) by summation of the first and second terms.

Abstract: According to one embodiment, a gate control circuit includes a controller, a delay circuit, a power circuit, a boosting circuit, a first transistor, and a control circuit. The controller outputs first and second control signals based on a control signal from outside. The delay circuit delays the first control signal. The power circuit is capable of controlling a power supply voltage to be output based on the delayed first control signal. The boosting circuit is capable of boosting and outputting an input voltage. The first transistor has one end connected to an output node of the boosting circuit, and the other end grounded. The control circuit is capable of controlling a gate voltage of the first transistor based on the second control signal.

Abstract: A driving device includes: a driving circuit operating with a single power supply in accordance with a driving signal; a first parallel circuit formed of a first capacitor and a first zener diode connected together in parallel, and having a first end connected to an output terminal of the driving circuit; a series circuit connected between a second end of the first parallel circuit and a ground of the driving circuit, and formed of a diode and a second parallel circuit (of a second capacitor and a second zener diode) connected to each other in series; and a resistor is connected between the second end of the first parallel circuit and the ground of the driving circuit. A voltage across the resistor is used as an output voltage for driving the insulated gate semiconductor element. A voltage across the first capacitor is superimposed negative-wise on the output voltage.

Abstract: An energy harvesting interface receives an electrical signal from an inductive transducer and outputs a supply signal. An input branch includes a first switch and a second switch connected in series between a first input terminal and an output terminal, and further a third switch and a fourth switch connected in series between a second input terminal and the output terminal. A first electrical-signal-detecting device coupled across the second switch detects a first threshold value of an electric storage current in the inductor of the transducer. A second electrical-signal-detecting device coupled across the fourth switch detects whether the electric supply current that flows through the fourth switch reaches a second threshold value lower than the first threshold value.

Abstract: In accordance with an embodiment, a synchronous N pulse burst generator includes an input for an intermediate frequency trigger signal and a signal path extending from the input. The signal path includes a series of N AND gates and an OR gate. Each AND gate is arranged to receive two inputs from the signal path. The signal path introduces a time delay between the two inputs received by each AND gate. A second input of the two inputs is inverted. The signal path introduces the time delay between successive AND gates from the series of N AND gates. An OR gate receives outputs from the series of N AND gates and outputs an A/D clock signal.

Abstract: Circuits, methods, and apparatus that may compensate for an incompatibility between connection detection schemes used by different interface circuits for different connector receptacles. One example may provide an active pull-down that normally provides a pull-down resistor and provides an open circuit for a period of time following a disconnection of an interface from a cable.

Abstract: An electrical power supply system has a fuel cell module and a battery. The fuel cell can be selectively connected to the battery system through a diode. The system preferably also has a current sensor and a controller adapted to close a contactor in a by-pass circuit around the diode after sensing a current flowing from the fuel cell through the diode. The system may also have a resistor and a contactor in another by-pass circuit around the diode. In a start-up method, a first contactor is closed to connect the fuel cell in parallel with the battery through the diode and one or more reactant pumps for the fuel cell are turned on. A current sensor is monitored for a signal indicating current flow through the diode. After a current is indicated, a by-pass circuit is provided around the diode.

Abstract: A delta-sigma modulator circuit comprising: an integrator circuit configured to produce an integrator output signal that represents an integration of an analog input signal, a comparator output signal and a periodic signal; a comparator circuit configured to produce the comparator output signal in response to a comparison of the integrator output signal with a first reference signal; and a periodic signal generation circuit configured to produce the periodic signal.

Abstract: A device (442) for producing a dynamic reference signal (UREF) for a control circuit for a power semiconductor switch comprises a reference signal generator (442) for providing a dynamic reference signal (UREF), which has a stationary signal level after elapse of a predefined time following a switching process of the power semiconductor switch, a passive charging circuit (450) which is configured to increase a signal level of the dynamic reference signal in reaction to a switching of a control signal of the power semiconductor switch from an OFF state to ON state for at least one part of the predefined time above the stationary signal level, in order to produce the dynamic reference signal and an output (A) for tapping the dynamic reference signal (UREF).

Abstract: A current clamp circuit includes a current-source circuit, a current-sense circuit, and a feedback circuit. The current-sense circuit includes a transistor, a resistive network, and a multiplexer. The transistor outputs a sensed current signal having a current that is equal to a current of an output signal provided by the current-source circuit. The feedback circuit limits the current of the sensed current signal and the output signal below a threshold current. The multiplexer modifies a resistance of the resistive network based on a first control signal. The multiplexer circuit and the feedback circuit are programmed using the first control signal and a second control signal when the transistor operates in a linear region and in a saturation region, respectively, to accurately output the sensed current signal.

Abstract: A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type. The semiconductor device further includes a polysilicon depleted gate shield disposed in the at least one trench, wherein the polysilicon depleted gate shield has a second conductivity type. The semiconductor device also includes a drift region disposed in the semiconductor substrate adjacent to at least one sidewall of the at least one trench, wherein the drift region has the first conductivity type, and a polysilicon gate disposed over the depleted gate shield in the at least one trench.

Abstract: A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type. The semiconductor device further includes a polysilicon depleted gate shield disposed in the at least one trench, wherein the polysilicon depleted gate shield has a second conductivity type. The semiconductor device also includes a drift region disposed in the semiconductor substrate adjacent to at least one sidewall of the at least one trench, wherein the drift region has the first conductivity type, and a polysilicon gate disposed over the depleted gate shield in the at least one trench.

Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.

Abstract: An inverter apparatus includes a first capacitor, a second capacitor, a first switch, a second switch, a third switch, a fourth switch, a first inductor and a second inductor. The first capacitor, the second capacitor, the first switch, the third switch and the first inductor form and have functions of a half bridge inverter. The first capacitor, the second capacitor, the second switch, the fourth switch and the second inductor form and have functions of a half bridge inverter. Therefore, the present invention obtains two kinds of voltages.

Abstract: A comparator includes a current mirror module, a comparison module and a buffering and outputting module. The current mirror module provides a bias current to the comparison module. The comparison module comprises a positive input end, a first negative input end and a second negative input end, the positive input end connects to an external terminal, the first negative input end and the second negative input end input a low threshold voltage and a high threshold voltage, respectively. The comparison module compares a voltage of the positive input end to the low threshold voltage and the high threshold voltage, and outputs a comparison result to the buffering and outputting module.

Abstract: The present application discloses a converter system, a driving circuit and a driving method for a semiconductor switch. The driving circuit includes a driving unit, a sampling unit and a selection unit. A plurality of turn-off driving units with different turn-off parameters is provided in the driving unit, and a turn-off driving unit having a turn-off parameter adaptive to the working state of the semiconductor switch is selected according to the working state of the semiconductor switch so as to turn off the semiconductor switch.

Abstract: A semiconductor device for driving a semiconductor switch, including a first transistor configured to extract gate charges of the semiconductor switch with a first extraction force, a comparator configured to compare gate voltage of the semiconductor switch with a threshold voltage to thereby output a first decision signal, an AND circuit configured to perform an AND operation on a gate voltage of the first transistor and the first decision signal to thereby output a second decision signal, a delay circuit configured to delay the second decision signal by a predetermined time and to output the delayed signal as a second control signal, and a second transistor configured to be turned-on, in response to the second control signal, the predetermined time after the first transistor is turned-on, to thereby extract the gate charges of the semiconductor switch with a second extraction force larger than the first extraction force.