Abstract: A display device includes a first substrate including a first sub-pixel area, a second sub-pixel area, and a third sub-pixel area; a first sub-pixel including a first light emitting element disposed in the first sub-pixel area; a second sub-pixel including a second light emitting element disposed in the second sub-pixel area; a third sub-pixel including a third light emitting element disposed in the third sub-pixel area; and a bank disposed between the first sub-pixel, the second sub-pixel, and the third sub-pixel and enclosing an emission area of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel. The bank includes a color bank including a color filter material that blocks light of colors emitted from the first light emitting element, the second light emitting element, and the third light emitting element.

Abstract: Provided are a display substrate, a manufacturing method thereof and a display apparatus. The display substrate includes a display region and a bezel region. The bezel region includes a first bezel and a second bezel oppositely disposed in a first direction, a third bezel and a fourth bezel oppositely disposed in a second direction, a first corner connecting a first bezel and a third bezel, a second corner connecting a second bezel and a third bezel, a third corner connecting a first bezel and a fourth bezel, and a fourth corner connecting a second bezel and a fourth bezel; at least one of a first corner to a fourth corner is an arced corner; a first direction is an extending direction of scanning signal wires in the display region, and a second direction is an extending direction of data signal wires in the display region.

Abstract: A semiconductor device includes a fin stack, a gate structure on the fin stack, a source region on a first side of the gate structure, a drain region on a second side of the gate structure opposite the first side, and a source contact extending to and connecting the source region. The source region and the drain region are asymmetric.

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material with vertical extensions that protrude to an interface with the channel material at an elevation proximate at least one source-side GIDL region. Slit structures extend through the stack structure to divide the structure into blocks of pillar arrays. A series of spaced, discrete pedestal structures are included along a base of the slit structures. Forming the microelectronic device structure may include forming a lateral opening through cell materials of the pillar, vertically recessing the channel material, and laterally recessing other material(s) of the pillar before forming the doped material in the broadened recesses.

Abstract: A semiconductor structure includes a substrate having a first dielectric constant, a porous semiconductor layer situated over the substrate, and a crystalline epitaxial layer situated over the porous semiconductor layer. A first semiconductor device is situated in the crystalline epitaxial layer. The porous semiconductor layer has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor layer reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer, and an electrical isolation region separating the first and second semiconductor devices.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a groove formed on the substrate, a channel layer structure grown under restriction of the groove structure, the channel layer structure being exposed from an upper surface of the substrate; a barrier layer covering the exposed channel layer structure, a two-dimensional electron gas and a two-dimensional hole gas respectively formed on a second face and a first face of the channel layer structure, and a source, a gate, and a drain formed on the first face/second face of the channel layer structure, and a bottom electrode formed on the second face/first face of the channel layer structure.

Abstract: According to the preparation method for a semiconductor structure provided in the present application, a selective epitaxial growth method is used, without etching the n-type semiconductor layer and the p-type semiconductor layer, thus avoiding problems such as uncontrollable etching depth and damaged etched surface, which effectively reduces gate leakage, maintains low resistance in a channel region, suppresses current collapse, and improves reliability and stability of a device.

Abstract: A method for forming a high electron mobility transistor includes the steps of providing a substrate, sequentially forming a buffer layer, a channel layer, a barrier layer, and a semiconductor gate layer on the substrate, forming a metal gate layer on the semiconductor gate layer, forming an insulating layer on the barrier layer, the semiconductor gate layer, and the metal gate layer and a passivation layer on the insulating layer, forming an opening through the passivation layer and the insulating layer to expose the metal gate layer, and forming a gate electrode on the passivation layer and filling the opening.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a conductive line structure and a memory unit. The conductive line structure is disposed in an array area and a periphery circuit area. The memory unit is disposed on the conductive line structure in the array area. The memory unit includes a lower electrode, a resistive switching layer, and an upper electrode. The lower electrode is disposed on the conductive line structure. The resistive switching layer is disposed on the lower electrode. The upper electrode is disposed on the resistive switching layer. The upper surface of the conductive line structure is in direct contact with the lower electrode.

Abstract: A DRAM includes a substrate, a plurality of first active regions disposed on the substrate and arranged end-to-end along the first direction, and a plurality of second active regions disposed between the first active regions and arranged end-to-end along the first direction. The second active regions respectively have a first sidewall adjacent to a first trench between the second active region and one of the first active regions and a second sidewall adjacent to a second trench between the ends of the first active regions, wherein the second sidewall is taper than the first sidewall in a cross-sectional view.

Abstract: A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.

Abstract: A semiconductor device comprises a substrate, a first hole-transporting layer over the substrate, a first electron-transporting layer on the first hole-transporting layer, and a second hole-transporting layer over the first electron-transporting layer. At least one of the first electron-transporting layer and the second hole-transporting layer has an organic component. The device is characterized by one of the following: a metal oxide layer present on the first electron-transporting layer, wherein a second electron-transporting layer is on the metal oxide layer, wherein the second hole-transporting layer is on the second electron-transporting layer, or the second hole transporting layer has a first p-doped hole-transporting surface present on the first electron-transporting, layer and a second p-doped hole-transporting surface facing away from the first p-doped hole-transporting surface, or the first electron-transporting layer is on a top surface and on sidewalls of the first hole-transporting layer.

Abstract: An electronic device is provided. The electronic device includes an optical sensing module that includes an optical sensor array. The optical sensor array includes at least one optical sensor, at least one transparent layer disposed on the optical sensor array, and a microlens array. The microlens array includes at least one microlens and is disposed on the transparent layer.

Abstract: According to one example, a method includes performing a first etching process on a fin stack to form a first recess and a second recess at a first depth, the first recess and the second recess on opposite sides of a gate structure that is on the fin stack. The method further includes depositing inner spacers within the first recess and the second recess. The method further includes, after depositing the inner spacers, performing a second etching process to extend a depth of the first recess to a second depth. The method further includes forming a dummy contact region within the first recess, forming a source structure within the first recess on the dummy contact region, and forming a drain structure within the second recess.

Abstract: The present disclosure discloses a display panel and a display device. According to the display panel, a fracture is provided on each gate signal line, so that the each gate signal line does not transversely extend through a display area. In this way, an abnormal invalid gate circuit area in a range of the display area at a left part below a dashed line formed by connecting the plurality of the fractures does not affect transmission of a gate signal, thereby reducing a reject ratio of products.

Abstract: The present disclosure relates to a method for manufacturing a pixel by: depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; defining an electrode by removing, by etching, part of the electrode layer resting on the insulating layer; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.

Abstract: A method of forming a semiconductor device includes forming a sacrificial layer over a first stack of nanostructures and an isolation region. A dummy gate structure is formed over the first stack of nanostructures, and a first portion of the sacrificial layer. A second portion of the sacrificial layer is removed to expose a sidewall of the first stack of nanostructures adjacent the dummy gate structure. A spacer layer is formed over the dummy gate structure. A first portion of the spacer layer physically contacts the first stack of nanostructures.

Abstract: Disclosed herein are lateral gate material arrangements for quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; and a gate above the quantum well stack, wherein the gate includes a gate electrode, the gate electrode includes a first material proximate to side faces of the gate and a second material proximate to a center of the gate, and the first material has a different material composition than the second material.

Abstract: The LED structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit includes a bonding layer formed on the substrate, a first doping type semiconductor layer formed on the bonding layer, a second doping type semiconductor layer formed on the first doping type semiconductor layer, a passivation layer formed on the second doping type semiconductor layer and a portion of the first doping type semiconductor layer; and an electrode layer formed on a portion of the passivation layer and contacting the second doping type semiconductor layer. The plurality of LED units include a first LED unit and a second LED unit adjacent to the first LED unit. The first doping type semiconductor layer of the first LED unit horizontally extends to the first doping type semiconductor layer of the second LED unit adjacent to the first LED unit, and the first LED unit and the second LED unit are individually functionable LED units.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. The memory-block regions comprise part of a memory-plane region. A pair of elevationally-extending walls are formed that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated. The pair of walls are one of (a) or (b), where: (a): in the memory-plane region laterally-between immediately-laterally-adjacent of the memory-block regions; and (b): in a region that is edge-of-plane relative to the memory-plane region. Through the horizontally-elongated trenches and after forming the pair of walls, sacrificial material that is in the first tiers is isotropically etching away and replaced with conducting material of individual conducting lines.