Abstract: A backplane, provides a physical layer level interconnection between a plurality of modules. The backplane includes a physical layer inplementation of an interconnection topology incorporated within one or more integrated circuits called interconnect chips. Incorporated on the interconnect chips are interconnect drivers and interconnect receivers for the physical layer implementation of the interconnection topology. These interconnect drivers and interconnect receivers provide point-to-point links between the physical layer implementation of the interconnection topology and the plurality of modules. Each point-to-point link may include two separate point-to-point link lines, one for an interconnect driver and one for an interconnect receiver. For the bus interconnection topology, alternately, each point-to-point link may be tri-level, including only a single point-to-point link line. The interconnection topology may be, for example, a bus topology, a ring topology or a circuit switched topology.

Abstract: A step-down circuit is incorporated in a large scale integrated circuit for producing an internal power voltage from an external power voltage, and the step-down circuit comprises a reference signal generating unit for producing a reference signal indicative of a target level for the internal power voltage, first and second voltage regulating units for regulating the internal power voltage to the target level, and a monitoring unit monitoring the voltage level of the power voltage and producing an enable signal in the standby mode of operation when the external power voltage exceeds a predetermined level, wherein the first and second voltage regulating units are selectively enabled depending upon mode of the large scale integrated circuit, i.e. an active mode and a standby mode, as well as the level of the external power voltage so that power consumption of the large scale integrated circuit is improved.

Abstract: A substrate potential generating circuit for a semiconductor integrated circuit in which, in addition to a conventional circuit for supplying a bias current to the substrate, at least two additional bias current supplying circuits are provided. With this configuration, when the substrate potential reaches its final level, the substrate bias current from the conventional circuit is interrupted to reduce the power consumption of the integrated circuit.