Abstract: A static memory cell including a pair of field-effect transistors, characterized by the provision of highly dielectric layers in combination with the field-effect transistors, wherein each of the highly dielectric layers is located directly on a polysilicon gate electrode layer formed on a silicon dioxide insulating layer bridging the channel region of each of the field-effect transistors. The gate electrode layer of one field-effect transistor is held in direct contact with the drain region of the other field-effect transistor and the two highly dielectric layers are covered with a polysilicon conductive layer electrically connected to a supply voltage source so that each field-effect transistor has its drain region connected to the supply voltage source through one dielectric layer and its gate electrode layer connected to the voltage source through the other dielectric layer.

Abstract: A semiconductor device is disclosed with a conductive on-chip shield film formed on its surface. The on-chip shield film is patterned in a manner substantially complementary to the pattern of the wiring layer of the semiconductor device so that the shield film does not cover portions of the semiconductor device which are covered by the wiring-pattern layer. In this manner, the on-chip shield film of the semiconductor device provides high resistance to electrostatic and electromagnetic induction while maintaining the ability of the device to withstand changes in ambient temperature.

Abstract: In a junction-shorting type PROM, including transistors, a highly doped region having the same conductivity type as a base is provided between a pair of memory cells. This region is a base contact region which commonly connects paired bases at a surface terminal connected to a word line. The base contact region also extends into the substrate, which is a collector, and prevents minority carries in each of the paired bases from diffusing into an adjacent base, and thus, prevents influence between the paired memory cells. The base contact region may be isolated from emitter regions by a narrow groove filled with insulation material. The narrow groove is deeper than the emitter regions but shallower than the substrate. A memory cell block composed of the paired cells and the base contact region is isolated at its circumference by the narrow groove.

Abstract: A vertical depletion mode power field effect transistor having a greatly increased drain-to-source breakdown voltage. The drain region is formed in the substrate and separated from the channel by a first insulative layer having apertures which allow the passage of electrical currents. The channel, which is formed between the first insulative layer and a second insulative layer parallel to the substrate surface, contains both a source region, formed by implantation of impurities of the same type as are used to form the drain region, and a gate region. In this configuration, the normally high voltage which exists between the gate and drain is imposed over a greater distance than in conventional depletion mode vertical FETs, so that this new configuration produces vertical power FETs having much higher breakdown voltages than do conventional depletion mode vertical FETs.

Abstract: An integrated transformer structure is disclosed. In one embodiment, the primary transformer winding is formed using dielectrically isolated (DI) technology so as to isolate high voltages applied to the transformer primary from other components in the substrate. Alternatively, conventional junction isolated technology may be used, where physical separation between the integrated transformer and other components may be provided. In accordance with the present invention, the primary winding comprises a planar spiral formed with a low-resistivity material and incorporated with the substrate. An insulating layer is then formed over the primary winding. A planar spiral configuration is also used to form the secondary winding, where the secondary may be formed of a deposited metal and is formed on top of the insulating layer so as to be directly above the primary winding. The result is an effective air-core transformer structure capable of isolating thousands of volts.

Abstract: An insulated gate field effect transistor of the depletion mode type has a recessed gate structure with opposed gate sections on opposite sides of adjacent bar-like structures defined in a channel region. An opposite conductivity-type island in the channel region is electrically connected to the transistor gate electrode. A voltage applied to the gate electrode generates an electric field effect which extends from the opposed gate sections into said bar-like structures creating opposed depletion regions which modulate channel current. The gate voltage simultaneously biases the island to enhance the gate electric field effect by removing minority charge carriers which would otherwise accumulate in the bar-like structures.

Abstract: A Zener diode (D) exhibiting subsurface breakdown includes a cathode (36) formed entirely within the emitter (22, 28) of a vertical PNP transistor (Q). The base (16) and collector (11) of the PNP transistor are resistively coupled to ground. The emitter of the PNP transistor functions as the anode of the Zener diode. Because of this, it is unecessary to provide an emitter contact. The PNP transistor compensates for changes in Zener breakdown voltage caused by changes in temperature. Because the PNP transistor is formed directly underneath the Zener diode, the temperature of the PNP transistor accurately tracks that of the Zener diode and therefore provides better temperature compensation. Also, because the cathode of the Zener diode is formed directly in the emitter of the PNP transistor, there is no lateral current flow and attendant voltage drop in the emitter of the PNP transistor.

Abstract: A semiconductor integrated circuit device of the master slice type which is suitable for use both in digital and analog circuits. The device includes a plurality of parallel basic elements, each including a plurality of p channel MOS transistors having gate electrodes connected commonly and source and drain regions separated from each other and a plurality of n channel MOS transistors having gate electrodes connected commonly and source and drain regions separated from each other. The source and drain regions of the p and n channel MOS transistors arranged in corresponding positions of the basic elements are common.

Abstract: A Schottky barrier diode and ohmic contact metallurgy which is especially suited for shallow-junction bipolar semiconductor devices. The metallurgy comprises a thin layer of an at least 95 atomic % pure Schottky metal disposed in the contact openings on a shallow-junction semiconductor device to a thickness of less than 850 angstroms. An electrically conducting barrier layer is then disposed over the thin Schottky metal layer, with the barrier layer being of a material which does not react with either the Schottky metal or the semiconductor material in the contact openings to thereby prevent semiconductor material from diffusing past the barrier layer. An electrical contact layer is then deposited over the barrier layer. The doping of the semiconductor material in the individual contact openings determines whether an ohmic contact or a Schottky barrier diode is formed. The resulting ohmic contact metal and Schottky barrier metal do not penetrate through to the shallow junction of the semiconductor device.

Abstract: A multiple wafer scale assembly apparatus includes first and second wafer scale assemblies connected to termination pins in such a fashion that the completed assembly is operatively self contained.

Abstract: In a semiconductor memory device, memory cells of a first column each comprising an N-channel FET are connected to a first bit line, and memory cells of a second column each comprising a P-channel FET are connected to a second bit line. The first bit line and the second bit line are connected to complementary terminals of a sense amplifier to form a folded-bit line pair. A work line is connected to the gate of the N-channel FET of one of the memory cells of the first column and to the gate of the P-channel FET of one of the memory cells of the second column. The word line is selectively provided with a first voltage to make conductive the N-channel FET connected thereto and to make nonconductive the P-channel FET connected thereto, or a second voltage to make conductive the P-channel FET connected thereto and to make nonconductive the N-channel FET connected thereto, or a third voltage to make nonconducitve both the N-channel FET and the P-channel FET connected thereto.

Abstract: A semiconductor device comprises a substrate, a semiconductor element mounted on the substrate, a cap having an opening smaller than the external size of the semiconductor element for covering the semiconductor element to provide a hermetic seal, and a heatsink member mounted on the cap to cover the opening and to make contact with the semiconductor element via the opening, so that heat generated by the semiconductor element is conducted directly to the heatsink member. A method of producing the semiconductor device comprises the steps of mounting the semiconductor element on the substrate, covering the semiconductor element by the cap which is fixed to the substrate, and mounting the heatsink member on the cap to cover the opening and to make contact with the semiconductor element via the opening.