Patents Examined by David Silver
  • Patent number: 7844434
    Abstract: A nonlinear electrical circuit dynamic model for different fuel cells is provided. The model provides a nonlinear electrical circuit equivalent, the parameters of which correspond to the particular fuel cell being modeled. The parameters can be theoretically or experimentally derived from the responses of the particular fuel cell. The resulting model can have impedances that are equivalent to that of the particular fuel cell, thereby capturing or providing a good approximation of the transient behavior of the particular fuel cell. More particularly, the resulting model can have impedances in the low frequency range less than 100 Hz that are equivalent to that of the particular fuel cell.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: November 30, 2010
    Assignee: Florida State University Research Foundation, Inc.
    Inventors: Yang Wang, Jian-ping Zheng
  • Patent number: 7844442
    Abstract: A system that includes a computing device configured to execute a software application and at least one remote user interface (UI) communicatively coupled to the computing device via a data communication network. The remote UI includes at least one hardware device such as a video, audio or user input/output (I/O) device. The computing device is further configured to emulate the hardware device locally and to redirect function calls generated by the software application for the emulated local hardware device to the remote UI for processing by the hardware device.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: November 30, 2010
    Assignee: Exent Technologies, Ltd.
    Inventor: Yoav M. Tzruya
  • Patent number: 7831418
    Abstract: Iterative (nondeterministic) optimization of aerodynamic and hydrodynamic surface structures can be accomplished with a computer software program and a system using a combination of a variable encoding length optimization algorithm based on an evolution strategy and an experimental hardware set-up that allows to automatically change the surface properties of the applied material, starting with the overall shape and proceeding via more detailed modifications in local surface areas. The optimization of surface structures may be done with a computing device for calculating optimized parameters of at least one (virtual) surface structure, an experimental hardware set-up for measuring dynamic properties of a specific surface structure, and an interface for feeding calculated parameters from the computing device to the experimental set-up and for feeding measured results back to the computing device as quality values for the next cycle of the optimizing step.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: November 9, 2010
    Assignee: Honda Research Institute Europe GmbH
    Inventors: Bernhard A. Sendhoff, Edgar Körner, Andreas Richter
  • Patent number: 7822586
    Abstract: Embodiments of the present invention include a computer program product including computer instructions that are executable to receive a set of process parameters, including fluid parameters and heat exchanger parameters, and determine a time for a dispense fluid to reach a target temperature. Additionally, the instructions can be executable to determine a set of process parameters that result in a time to reach the target temperature of below a predefined limit. According to another embodiment of the present invention, a set of computer instructions can calculate the time it takes for a dispense fluid to reach a target temperature for predictive flow control of a heating/cooling fluid.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: October 26, 2010
    Assignee: Entegris, Inc.
    Inventors: Qunwei Wu, Joseph E. Smith
  • Patent number: 7822591
    Abstract: A logic circuit model conversion apparatus includes a first analysis unit which analyzes a model in which a logic circuit of a register transfer level has been coded and outputs simultaneous blocks and an analysis result, a creating unit which creates a common execution frequency group that is a set of codes whose execution frequency becomes common, based on the simultaneous blocks and analysis result, a second analysis unit which analyzes the common execution frequency group and creates a formula of a general term to derive a predetermined value of each register, a third analysis unit which analyzes a mutual relationship between the common execution frequency groups and derives an execution frequency of each common execution frequency group up to a predetermined time, and a deriving unit which derives a value of each of the registers at the predetermined time from the formula of the general term and execution frequency.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: October 26, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoshi Otsuki, Nobuhiro Nonogaki
  • Patent number: 7818150
    Abstract: A method is disclosed that preparing a discrete event simulation model of a production network is provided including a client and a plurality of servers connected by a network comprising the steps of initiating a single business function trace test on the production network; gathering network flow trace data from the network; deriving a transaction summary from the network flow trace data; initiating a single business function load test on the production network; gathering resource data from the plurality of servers; normalizing the resource data; gathering web log data from at least one server from the plurality of servers; calculating a number of business functions running on the production network; calculating a consumption of resources used by the plurality of servers; calculating a business function cost associated with the consumption of resources; creating a business function profile from the transaction summary and the business function cost; and building a discrete event simulation model from the bus
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: October 19, 2010
    Assignee: HyPerformix, Inc.
    Inventors: Paul T. Barnett, Timothy E. Wise, Allan Drew Clarke, Richard Gimarc, James Reynolds
  • Patent number: 7818161
    Abstract: An information processing apparatus includes: a processor configured to run an operating system; a reconfiguration module configured to rewrite a capability pointer of a PCI device configuration to set a controller compatible of controlling a non-UART device to be incompatible; a virtualization module configured to virtualize one or more UARTs; and a recognition module configured to cause the operating system to recognize the UARTs virtualized by the virtualization module by altering hardware information.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: October 19, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuyoshi Nishida
  • Patent number: 7813907
    Abstract: An embodiment of the present invention may be a system or method for simulating the flow of a single-phase fluid flow. Markers represent a moving fluid boundary of the single-phase fluid at a first point in time. The moving fluid boundary separates a simulation space into a fluid space and a non-fluid space. The single-phase fluid inhabits the fluid space. A signed distance function is evaluated at points surrounding the moving fluid boundary based upon markers. The curvature of the moving fluid boundary based on the signed distance function is evaluated near the markers in the non-fluid space. The curvature is not evaluated at the moving fluid boundary. The velocity of the fluid is calculated based upon the curvature of the level set in the non-fluid space. Update the position of the moving fluid boundary at a second point in time based on the velocity of the fluid.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: October 12, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Jie Zhang, Jiun-Der Yu
  • Patent number: 7774172
    Abstract: A system and method of exposing debugging information in a graphical modeling and execution environment is disclosed. The present invention allows a user to view debugging information in the same window as the graphical view of the model being executed. Debugging data is associated with relevant components of the model displayed in the graphical view. A separate execution list view shows the methods called during the execution of the block diagram in the current time step up until the current point in execution. User-set breakpoints and conditional breakpoints may be set in both the model view and the execution list view. Values may be obtained for all of the displayed methods. The debugging tool may be implemented by using it in conjunction with a graphical modeling and execution environment, such as a block diagram environment or state diagram environment.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: August 10, 2010
    Assignee: The MathWorks, Inc.
    Inventors: Mehmet Yunt, Murali Yeddanapudi, Sanjai Singh, John Ciolfi
  • Patent number: 7761279
    Abstract: In one embodiment of the invention, a method of simulating a circuit is disclosed including simulating an analog component of the circuit over a first simulation time period with a first envelope simulation; adaptively switching from simulating the analog component with the first envelope simulation to simulating the analog component with a transient simulation over a second simulation time period; and adaptively switching from simulating the analog component with the transient simulation to simulating the analog component with a second envelope simulation over a third simulation time period. The adaptive switching from the first envelope simulation to the transient simulation may be in response to the envelope simulation accuracy falling below a predetermined level of accuracy in comparison with a transient simulation or in response to the second simulation time period including expected digital transitions where one or more digital events may occur to change the analog input signals to the analog component.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: July 20, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Qian Cai, Dan Feng
  • Patent number: 7761284
    Abstract: A data protection and storage system includes an array of disk drives for data storage. Data is received for storage on the disk drive via an interface that is configured to emulate a tape drive interface. A virtual tape data structure is created and stored on the disk drives. The allocated capacity of the virtual tape is dynamically and transparently alterable in response to data storage demand within the virtual tape.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: July 20, 2010
    Assignee: Overland Storage, Inc.
    Inventors: John E. Matze, Michael H. Reider, Kenneth David Geist, Daniel Davies
  • Patent number: 7739097
    Abstract: A hardware emulation system is disclosed which reduces hardware cost by time multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The hardware emulation system comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces through the use of multiplexing.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: June 15, 2010
    Assignee: Quickturn Design Systems Inc.
    Inventors: Stephen P. Sample, Mikhail Bershteyn, Michael R. Butts, Jerry R. Bauer
  • Patent number: 7739081
    Abstract: Methods for modeling and executing systems in a linearly-implicit formulation of ordinary differential equations (ODEs) or differential algebraic equations (DAEs) are provided in modeling environments. The modeling environments may include block diagram modeling environments, such as time-based block diagram modeling environments. The block diagram modeling environments may include or be coupled to other modeling environments, such as physical modeling environments, so that models created in other modeling environments may also be introduced and solved in the linearly-implicit formulation of ODEs or DAEs in the block diagram modeling environments. Models describing the systems in the linearly-implicit formulation of ODEs or DAEs may also be created directly by users using user-defined blocks in the block diagram modeling environments. The present invention provides solvers for solving the system described in the linearly-implicit formulation of DAEs as well as ODEs in the block diagram modeling environment.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: June 15, 2010
    Assignee: The Math Works, Inc.
    Inventors: Jacek Kierzenka, Jeff Wendlandt
  • Patent number: 7734457
    Abstract: The present invention is directed to a method and system that includes comparing first and second models. A comparison model may be generated that indicates differences between the first model and the second model. A notification manager is used to register the comparison model as a subscriber of the first and second models. The first model is updated to reflect a first designated change. Upon successful completion of the first designated change, the notification manager is used to issue a notification of the designated change to the first model. At least the comparison model is updated to reflect the first designated change, and the comparison model is displayed on a client.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: June 8, 2010
    Assignee: Computer Associates Think, Inc.
    Inventor: Tad A. Deffler
  • Patent number: 7729898
    Abstract: A heterogeneous device including multiple types of resources is provided to implement multiple logic functions. Logic functions are provided with multiple configuration options. In one example, an optimal set of configuration options along with a target device are selected using cost and resource availability information associated with multiple heterogeneous programmable chips and the configuration options provided with the logic blocks.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: June 1, 2010
    Assignee: Altera Corporation
    Inventor: Craig Lytle
  • Patent number: 7716034
    Abstract: A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: May 11, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Manisha Agarwala, Lewis Nardini, John M. Johnsen, Maria B. H. Gill, Jose L. Flores
  • Patent number: 7716035
    Abstract: PCI simulation component has an initialization component, a configuration space simulator and a memory-mapped I/O space simulator. The initialization component can claim an amount of memory by modifying the amount of memory that an operating system has available to it. The initialization component further identifies to the operating system that at least some of the claimed memory resides on a PCI bus. The configuration space simulator causes the operating system to accept that the simulated PCI device is present in the system.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: May 11, 2010
    Assignee: Microsoft Corporation
    Inventors: Jacob Oshins, Brandon Allsop
  • Patent number: 7711533
    Abstract: A distributed network of interactive agents is provided wherein remote agents interact with a central computer and with one another through an object based parallel modeling language and/or an aggregate modeling language using an open client-server architecture, which enables many users to control the behavior of individual objects or agents and to view the aggregated results on a central computer. This network of agents is integrated with a powerful suite of modeling, analysis and display tools that together give agents the capacity to “fly” the system in intuitive mode, to reflect on the emergent result of their simulation and, also, to encode their strategies as rules which the system can then run independently.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: May 4, 2010
    Inventors: Uri Wilensky, Walter M. Stroup
  • Patent number: 7702490
    Abstract: A method, system and computer program product pertained to adaptive discretization refinement of shell structure is disclosed. The adaptive mesh-free model is based on a technique for dividing the critical area into a finer model. The present invention is a method for enabling adaptive mesh-free shell structure in a time-domain analysis, the method comprises: defining the mesh-free shell structure by a structural geometry description file including a plurality of nodes and a reference 3-D mesh, which includes a plurality of shell elements, mapping the 3-D reference mesh into a 2-D parametric plane, wherein the 2-D parametric mesh includes a plurality of integration cells corresponding to the plurality of shell elements, solving structural responses at current solution cycle using mesh-free mathematical approximations pertaining to each of the plurality of integration cells, performing adaptive discretization refinement for the plurality of the integration cells.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: April 20, 2010
    Assignee: Livermore Software Technology Corporation
    Inventors: Cheng-Tang Wu, Yong Guo
  • Patent number: 7702498
    Abstract: A method of tracing data processor activity includes trace data markers indicating initiation and termination of at least one trace function at a specified program counter address and emulation pause related markers indicating initiation and termination of an emulation halt state at a specified program counter. Each emulation pause related marker includes a conflict bit indicating the presence or absence of a simultaneous trace data marker having a different program counter address.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: April 20, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Manisha Agarwala