Abstract: A method and an apparatus are provided for manufacturing an active matrix device including a top gate type TFT. A manufacturing process of the top gate type TFT includes the steps of forming an oxide film on the inner wall of a CVD processing chamber and arranging a substrate having source and drain electrodes formed thereon in the processing chamber. Additional steps include doping the source and drain electrodes with P, and forming an a-Si layer and a gate insulating film in the processing chamber. Furthermore, an apparatus is provided for manufacturing an active matrix device including a top gate type TFT having the inner surface of the processing chamber coated with the oxide film.

Abstract: A method of manufacturing a semiconductor device is disclosed, which comprises setting a stencil mask above a substrate to be processed in confronting to the substrate, the stencil mask having an opening, and irradiating the substrate with charged particles through the opening of the stencil mask, while adjusting a potential difference between the stencil mask and the substrate depending on a value of a current flowing between the substrate and the stencil mask.

Abstract: A method is provided including, after joining a wiring substrate and an element substrate, separating a second substrate of the element substrate from a semiconductor element, and electrically coupling an element-side terminal that has been exposed by the separation to a wiring-side terminal disposed outside the semiconductor element by electroless plating.

Abstract: A method for forming quantum dots includes forming a superlattice structure that includes at least one nanostrip protruding from the superlattice structure, providing a quantum dot substrate, transferring the at least one nanostrip to the quantum dot substrate, and removing at least a portion of the at least one nanostrip from the substrate. The superlattice structure is formed by providing a superlattice substrate, forming alternating layers of first and second materials on the substrate to form a stack, cleaving the stack to expose the alternating layers, and etching the exposed alternating layers with an etchant that etches the second material at a greater rate than the first to form the at least one nanostrip.

Abstract: A process and system for processing a thin film sample, as well as the thin film structure are provided. In particular, a beam generator can be controlled to emit successive irradiation beam pulses at a predetermined repetition rate. Each irradiation beam pulse may be masked to define a first plurality of beamlets and a second plurality of beamlets. The first and second plurality of beamlets of each of the irradiation pulses being provided for impinging the film sample and having an intensity which is sufficient to at least partially melt irradiated portions of the section of the film sample. A particular portion of the section of the film sample is irradiated with the first beamlets of a first pulse of the irradiated beam pulses to melt first areas of the particular portion, the first areas being at least partially melted, leaving first unirradiated regions between respective adjacent ones of the first areas, and being allowed to resolidify and crystallize.

Abstract: A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum nitride barrier layer, on a substrate by using an atomic layer deposition process (a vapor deposition process that includes a plurality of deposition cycles) with a refractory metal precursor compound, an organic amine, and an optional silicon precursor compound.

Abstract: A gate pattern having a critical dimension after an etching process of 60-70nm may be formed using an ArF photoresist as an etching mask by a method including sequentially forming a gate oxide layer, a gate electrode layer, an anti-reflection coating layer, and an ArF photoresist layer on a semiconductor wafer; forming a photoresist pattern by exposing and developing the ArF photoresist layer; etching the anti-reflection coating layer using the photoresist pattern as an etching mask; removing an oxide layer formed during etching of the anti-reflection coating layer; etching the gate electrode layer; and over-etching a remaining gate electrode layer.

Abstract: A solder is deposited on the backside of a wafer. The wafer can be pre-deposited with a barrier layer such as a titanium base and other materials. Deposition is carried out by electroplating, electroless plating, chemical vapor deposition, and physical vapor deposition. The solder-deposited die is bonded with a heat spreader that did not require a pre-deposited solder.

Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.

Abstract: A method of fabricating a flexible thin film transistor array substrate is provided. First, a rigid substrate is provided, and a polymer material layer is coated on the rigid substrate. Then, an insulating layer is coated over the polymer material layer by a spin coating process. The insulating layer covers the sides of the polymer material layer. Thereafter, a thin film transistor array is formed over the insulating layer. Then, the polymer material layer having the thin film transistor array is separated from the rigid substrate.

Abstract: A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a CVD process. The diffusion barrier layer is of particular utility in conjunction with tungsten or tungsten silicide conductive layers formed by CVD.