Patents Examined by David Yi
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Patent number: 11704048Abstract: An electronic device includes a controller; and a non-transitory computer-readable storage medium configured to store operation codes for causing the controller to execute processes. The non-transitory computer-readable storage medium includes a plurality of memory blocks. The processes include grouping the plurality of memory blocks into a plurality of super blocks; selecting a first super block among the plurality of super blocks depending on one or more logical addresses corresponding to write-requested data, and writing the data; and mapping the first super block to a first logical address range. The first logical address range is configured by successive addresses corresponding to a super block size, and a start address of the successive addresses is a start logical address of the one or more logical addresses.Type: GrantFiled: January 12, 2021Date of Patent: July 18, 2023Assignee: SK hynix Inc.Inventors: Seok Hoon Jung, In Woong Heo
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Patent number: 11704050Abstract: A memory system which stores a journal including mapping change information, either in a first memory area or a second memory area, depending on available space of a memory device included in the memory system, being greater than a threshold.Type: GrantFiled: June 8, 2021Date of Patent: July 18, 2023Assignee: SK hynix Inc.Inventors: Jin Pyo Kim, Woo Young Yang
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Patent number: 11693586Abstract: The present disclosure relates to designating or allocating static and dynamic SLC blocks between a non-write burst free block pool and a write burst free block pool. In some embodiments, a free block pool can be utilized by a host for write burst operations and/or non-write burst operations. In these embodiments, the over provisioning portion of the memory sub-system can be designated into a plurality of portions.Type: GrantFiled: June 24, 2021Date of Patent: July 4, 2023Assignee: Micron Technology, Inc.Inventors: Xiangang Luo, Jianmin Huang
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Patent number: 11693571Abstract: According to one embodiment, there is provided a memory system including a non-volatile memory and a controller. The non-volatile memory includes a plurality of physical blocks. The controller is connected to any of the plurality of physical blocks via a plurality of channels. The controller is configured to construct a plurality of logical blocks and, read or write data from or into any of the plurality of logical blocks constructed. The logical blocks are management units in which any of the physical blocks is grouped across the plurality of channels. The controller is configured to construct the plurality of logical blocks so that a first number of defective blocks and a second number of pseudo defective blocks for shortfall defective blocks with respect to a target number of defective blocks are distributed into the plurality of logical blocks.Type: GrantFiled: December 9, 2021Date of Patent: July 4, 2023Assignee: Kioxia CorporationInventor: Akira Shimizu
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Patent number: 11687279Abstract: A storage device includes: a storage controller to receive data from a host device, and to store the data in storage memory; and a reconfigurable integrated circuit communicably connected to the storage controller, and to accelerate logic operations executed on the data stored in the storage memory, the reconfigurable integrated circuit including: a first logic block to execute a static logic operation from among the logic operations; a second logic block to execute one or more dynamic logic operations from among the logic operations; and a plurality of memory buffers configured to store inputs and outputs of the first and second logic blocks.Type: GrantFiled: March 20, 2020Date of Patent: June 27, 2023Assignee: Samsung Electronics Co., Ltd.Inventor: Pankaj Mehra
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Patent number: 11687263Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a request from a requester for a superblock, determine that one or more blocks of a die of the superblock are expected to fail, and either replace the one or more blocks of the die with another one or more blocks from a different die or add the another one or more blocks from the different die and disable the one or more blocks of the die, and provide the superblock to the requester. The superblock provided to the requester is erased prior to the providing and is the same size as an original superblock.Type: GrantFiled: December 1, 2021Date of Patent: June 27, 2023Assignee: Western Digital Technologies, Inc.Inventors: Vineet Agarwal, Chaitanya Kavirayani, Ratanvel Nadar
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Patent number: 11681475Abstract: Techniques for processing an access request and updating a storage system are provided. For instance, a method comprises: receiving an access request for an object associated with a storage system, the storage system including a plurality of physical nodes, each of the plurality of physical nodes including at least one set of virtual units, each set of virtual units including at least one virtual unit; determining, from a plurality of sets of virtual units included in the plurality of physical nodes of the storage system, a target set of virtual units associated with the object; and determining, from the target set of virtual units, a target virtual unit corresponding to the object. With the technical solution of the present disclosure, not only a set of virtual units on a physical node may be easily split and merged, but also huge computing resources that need to be allocated may be saved, so better user experience may be brought about at a lower cost.Type: GrantFiled: February 4, 2022Date of Patent: June 20, 2023Assignee: EMC IP HOLDING COMPANY LLCInventors: Lu Lei, Ao Sun
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Patent number: 11681443Abstract: A data storage system includes a head node and mass storage devices. The head node is configured to store volume data and flush volume data to the mass storage devices. Additionally, the head node is configured to determine a quantity of data partitions and/or parity partitions to store for a chunk of volume data being flushed to the mass storage devices in order to satisfy a durability guarantee. For chunks of data for which complete copies are also stored in an additional data storage system, the head node is configured to reduce the quantity of data partitions and/or parity partitions stored such that required storage space is reduced while still ensuring that the durability guarantee is satisfied.Type: GrantFiled: August 28, 2020Date of Patent: June 20, 2023Assignee: Amazon Technologies, Inc.Inventors: Sriram Venugopal, Kun Tang, Norbert Paul Kusters, Jianhua Fan
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Patent number: 11681592Abstract: Obtaining a consistent set of snapshots of a group of storage volumes includes obtaining a plurality of snapshots, each of the snapshots being for one of the volumes, determining if there are any specific write operations to at least one volume that occurred after obtaining a first one of the snapshots and before obtaining a last of the snapshots, if there are any specific write operations, discarding the plurality of snapshots, and, if there are no specific write operations, designating the plurality of snapshots as the consistent set of snapshots. Obtaining a consistent set of snapshots may include repeatedly obtaining a plurality of snapshots and determining if there are specific write operations until either a particular condition is met or there are no specific write operations determined. The particular condition may be exceeding a predetermined number of iterations or a predetermined time limit.Type: GrantFiled: July 9, 2020Date of Patent: June 20, 2023Assignee: EMC IP Holding Company LLCInventors: Evan G. Jones, Douglas E. LeCrone, Brett A. Quinn
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Patent number: 11681469Abstract: The disclosed embodiments are related to storing critical data in a memory device such as Flash memory device. In one embodiment, a method performed by a controller of a memory device comprises receiving a critical operation from a host processor, the critical operation accessing a memory array; retrieving a temperature value of the memory array from a temperature sensor; and conditionally processing the critical operation based on the temperature value.Type: GrantFiled: February 22, 2021Date of Patent: June 20, 2023Assignee: Micron Technology, Inc.Inventor: Gil Golov
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Patent number: 11675527Abstract: A memory system may include: a nonvolatile memory device suitable for storing user data and meta data of the user data; and a controller suitable for uploading at least some of the meta data to a host. When the size of a free space of a storage space of the host, allocated to store the uploaded meta data, is equal to or less than a preset value, the controller may upload hot meta data to the host according to the number of normal read requests received from the host and the ratio of the normal read requests.Type: GrantFiled: February 1, 2021Date of Patent: June 13, 2023Assignee: SK hynix Inc.Inventor: Kwang Su Kim
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Patent number: 11675528Abstract: Aspects of a storage device including a memory and a controller are provided. The memory includes a plurality of non-volatile memory packages coupled to the switch, in which each non-volatile memory package includes a plurality of non-volatile memory dies. The controller can select a non-volatile memory package with the switch. The controller can establish a data channel connection between the selected non-volatile memory package and the controller via the switch. In some aspects, the selected non-volatile memory package is transitioned into an active mode and one or more non-selected non-volatile memory packages are each transitioned into a standby mode. The controller also can perform one or more storage device operations with one or more non-volatile memory dies of the plurality of non-volatile memory dies within the selected non-volatile memory package. Thus, the controller may facilitate a switch based ball grid array extension, thereby improving memory capacity of the storage device.Type: GrantFiled: March 29, 2021Date of Patent: June 13, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Akhilesh Yadav, Ramanathan Muthiah, Eldhose Peter
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Patent number: 11669264Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory is configured to store an address translation table and a data map. In a case where an invalidation command for invalidating the data written in the non-volatile memory is received from the host, the controller is configured to update the address translation table and the data map based on the invalidation command. A response to the invalidation command is transmitted to the host after the address translation table is updated and before the data map is updated.Type: GrantFiled: March 15, 2021Date of Patent: June 6, 2023Assignee: Kioxia CorporationInventors: Yuki Sasaki, Shinichi Kanno
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Patent number: 11669466Abstract: The present disclosure provides methods, apparatus, and systems for implementing and operating a memory module, for example, in a computing that includes a network interface, which may be coupled to a network to enable communication with a client device, and host processing circuitry, which may be coupled to the network interface via a system bus and programmed to perform first data processing operations based on user inputs received from the client device. The memory module may be coupled to the system bus and include memory devices and a memory controller coupled to the memory devices via an internal bus. The memory controller may include memory processing circuitry programmed to perform a second data processing operation that facilitates performance of the first data processing operations by the host processing circuitry based on context of the data block indicated by the metadata.Type: GrantFiled: April 29, 2022Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventor: Richard C. Murphy
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Patent number: 11663140Abstract: A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, a non-volatile memory, and a controller. The controller is configured to receive a read command to read a data word from an address of the array and decode the address to generate a decoded address. The controller is further configured to retrieve response data from the decoded address of the array, retrieve a location indicia corresponding to the decoded address from the non-volatile memory, and verify that the location indicia corresponds to the address. The controller can optionally be further configured to indicate an error if the location indicia does not correspond to the address.Type: GrantFiled: August 9, 2021Date of Patent: May 30, 2023Assignee: Micron Technology, Inc.Inventor: Alberto Troia
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Patent number: 11662935Abstract: Methods, systems, and devices for improved data management for memory are described. An apparatus may include a memory array including one or more blocks of memory cells. Data read from a block of memory cells may be written to a buffer, to support providing the data to a host system or modification of the data by the host system. If a quantity of read commands performed at the block of memory cells satisfies a threshold, the data may be written from the buffer to a different block of memory cells, rather than the block from which the data was previously read.Type: GrantFiled: August 12, 2021Date of Patent: May 30, 2023Assignee: Micron Technology, Inc.Inventors: Luigi Esposito, Alberto Sassara, Paolo Papa, Massimo Iaculo
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Patent number: 11656795Abstract: A command is received from a host regarding accessing an NVMe dispersed namespace in a metro cluster configuration of storage arrays. A namespace group state corresponding to the host and the port is determined and returned to the host. The namespace group state indicates whether the specific communication path between the host and the port is optimized or non-optimized. The namespace group state indicates that the communication path is non-optimized where the host is not located at the same location as the storage array, and that the communication path is optimized where the host is located at the same location as the storage array and the node of the storage array is a preferred node for processing I/O directed to the NVMe dispersed namespace from hosts located in the same location as the storage array.Type: GrantFiled: January 21, 2021Date of Patent: May 23, 2023Assignee: EMC IP Holding Company LLCInventors: Dmitry Nikolayevich Tylik, David L. Black, Marina Shem Tov, Mukesh Gupta
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Patent number: 11650737Abstract: A computer-implemented method comprises initializing a plurality of segment lists. Each segment list of the plurality of segment lists corresponds to a respective one of a plurality of disk drives. Each segment list divides storage space of the respective disk drive into a plurality of segments. The method further comprises, for each of the plurality of disk drives, identifying one or more candidate segments from the plurality of segments; calculating a respective segment distance variance for one or more combinations of identified candidate segments. Each combination of identified candidate segments includes one candidate segment for each of the plurality of disk drives. The method further comprises selecting a combination of the one or more combinations of identified candidate segments having the smallest respective segment distance variance; and storing data on the plurality of disk drives according to the selected combination of identified candidate segments.Type: GrantFiled: November 26, 2019Date of Patent: May 16, 2023Assignee: International Business Machines CorporationInventors: Lin Feng Shen, Ji Dong Li, Yong Zheng, Guang Han Sui, Shuo Feng, Hai Zhong Zhou, Yu Bing Tang, Wu Xu
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Patent number: 11650748Abstract: In a method for offloading data processing into computational storage, a request to offload data computation into computational storage is received. One or more transactions to encapsulate the request are prepared. One or more write requests are generated based on the one or more transactions, and the one or more transactions are stored into one or more journals. A set of transactions is extracted from the one or more journals. A subset of the set of transactions is received at an eBPF subsystem, where the subset corresponds to one or more computation requests. Information from a file is extracted, where the information corresponds to one or more logical block addresses (LBAs). The one or more computation requests are performed on the one or more LBAs using the subset of the set of transactions, and an indication corresponding to the performed computation requests is generated.Type: GrantFiled: July 21, 2022Date of Patent: May 16, 2023Assignees: Lemon Inc., Beijing Youzhuju Network Technology Co Ltd.Inventors: Viacheslav Dubeyko, Jian Wang
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Patent number: 11650938Abstract: A device-capability-based locking key management system includes a key management system coupled to a server device via a network. The server device includes storage devices coupled to a remote access controller device. The remote access controller device identifies each of the storage devices, and then identifies a key management profile for each of the storage devices. A first key management profile identified for at least one first storage device is different from a second key management profile identified for at least one second storage device. The remote access controller device then uses the respective key management profile identified for each of the storage devices to create a respective key management sub-client for each of the storage devices, and each respective key management sub-client communicates with the key management system to provide a locking key for its respective storage device.Type: GrantFiled: January 25, 2019Date of Patent: May 16, 2023Assignee: Dell Products L.P.Inventors: Rama Rao Bisa, Sushma Basavarajaiah, Mukund P. Khatri, Chandrashekar Nelogal, Chitrak Gupta, Manjunath Am