Patents Examined by David Zarneke
  • Patent number: 11127671
    Abstract: Power semiconductor module, including a base plate with at least one substrate located on the base plate, wherein an electronic circuit is provided on the at least one substrate, wherein located on the at least one substrate are electrical connectors comprising a DC+ power terminal, a DC? power terminal and an AC power terminal and further a control connector, wherein the power semiconductor module is designed as a half-bridge module including a first amount of switching power semiconductor devices and a second amount of switching power semiconductor devices, wherein the base plate includes a contact area, a first device area and a second device area, wherein the contact area is positioned in a center of the base plate such, that the first device area is positioned at a first side of the contact area and that the second device area is positioned at a second side of the contact area, the second side being arranged opposite to the first side, wherein the DC+ power terminal, the DC? power terminal, the AC power
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: September 21, 2021
    Assignee: ABB Power Grids Switzerland AG
    Inventors: Samuel Hartmann, Dominik Truessel
  • Patent number: 11121113
    Abstract: A bonding apparatus includes a holding element, holding element actuators, sensors, a controller and bond force adjusting actuators. In use, the holding element holds an electrical component and is moved by the holding element actuators in one or more actuating directions to contact the electrical component with a base member. The sensors measure reaction forces exerted on the holding element in response to contact between the electrical component and the base member. The controller determines bond forces to be exerted on actuating areas of the holding element during a bonding process based on the measured reaction forces, and the bond force adjusting actuators exert these bond forces on the actuating areas of the holding element during the bonding process, so as to adjust a tilt of the electrical component relative to the base member.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: September 14, 2021
    Inventors: Ming Yeung Wan, Wai Kin Cheung, Yu Fu Cheung
  • Patent number: 11121091
    Abstract: A method and device for the alignment of substrates that are to be bonded. The method includes detecting and storing positions of alignment mark pairs located on surfaces of the substrates, and aligning the substrates with respect to each other in accordance with the detected positions.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 14, 2021
    Assignee: EV Group E. Thallner GmbH
    Inventor: Thomas Wagenleitner
  • Patent number: 11101417
    Abstract: A printed structure includes a destination substrate comprising two or more contact pads disposed on or in a surface of the destination substrate, a component disposed on the surface, and two or more electrically conductive connection posts. Each of the connection posts extends from a common side of the component. Each of the connection posts is in electrical and physical contact with one of the contact pads. The component is tilted with respect to the surface of the destination substrate. Each of the connection posts has a flat distal surface.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: August 24, 2021
    Assignee: X Display Company Technology Limited
    Inventors: Christopher Andrew Bower, Matthew Alexander Meitl, Ronald S. Cok, Salvatore Bonafede, Brook Raymond, Andrew Tyler Pearson
  • Patent number: 11099413
    Abstract: According to one embodiment, a display device includes a first basement, a first folding line and a second folding line. The first basement has a first area which is a display area including a display element, and a second area and a third area which are non-display areas and are adjacent to the first area. The first folding line is located at a border of the first area and the second area. The second folding line is located at a border of the first area and the third area. The first folding line extends in a first direction, and the second folding line extends in a second direction intersecting the first direction.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: August 24, 2021
    Assignee: Japan Display Inc.
    Inventors: Yoshiro Aoki, Toshiya Yamazaki, Kazunori Yamaguchi, Toshihiro Yanagi, Yoshitoshi Kida, Kazuhiro Nishiyama, Shinichiro Oka, Hiroyuki Kimura, Takashi Nakamura
  • Patent number: 11094562
    Abstract: A semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device may comprise a semiconductor die having a top major surface that has one or more electrical contacts formed thereon, an opposing bottom major surface, and side surfaces; a molding material encapsulating the top major surface, the bottom major surface and the side surfaces of the semiconductor die, wherein the molding material defines a package body that has a top surface and a side surface; wherein the plurality of electrical contacts are exposed on the top surface of the package body and a metal layer is arranged over and electrically connected to the electrical contacts and wherein the metal layer extends to and at least partially covers a side surface of the package body.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: August 17, 2021
    Assignee: Nexperia B.V.
    Inventors: Leung Chi Ho, Pompeo V. Umali, Shun Tik Yeung
  • Patent number: 11094722
    Abstract: An image sensor package according to an embodiment of the present technology includes: a solid-state image sensor; a transparent substrate; and a package substrate. The solid-state image sensor has a light-receiving surface including a light-reception unit and a first terminal unit, and a rear surface opposite to the light-receiving surface. The transparent substrate faces the light-receiving surface. The package substrate includes a frame portion, a second terminal unit, and a supporting body. The frame portion has a joint surface to be joined to the transparent substrate and includes a housing portion housing the solid-state image sensor. The second terminal unit is to be wire-bonded to the first terminal unit, the second terminal unit being provided in the frame portion. The supporting body is provided in a peripheral portion of the light-receiving surface or at a center portion of the rear surface and partially supports the light-receiving surface or the rear surface.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: August 17, 2021
    Assignee: Sony Corporation
    Inventors: Tsuyoshi Watanabe, Yutaka Ootaki
  • Patent number: 11081489
    Abstract: A semiconductor structure is disclosed, which comprises a substrate, a bit line (BL) stack feature and a BL spacer. The substrate has a cell area and a periphery area defined thereon. The bit line stack feature formed over an active region in the cell area, comprises a buffer liner having a U-shaped profile that opens upwardly in a cross section thereof and defining an inner surface, a BL conductor disposed in the U-shaped profile on the inner surface, and a capping layer over the BL conductor. The BL spacer covers sidewall surfaces of the BL stack feature.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: August 3, 2021
    Inventors: Chang-Hyeon Nam, Injoon Yeo
  • Patent number: 11075258
    Abstract: The present disclosure relates to the field of display technologies, and provides a display substrate, a manufacturing method thereof, a corresponding display panel and an encapsulation method for the same. The display substrate includes a base plate comprising a display area and an encapsulation area surrounding the display area, and an insulating layer and a plurality of wires located on the base plate. The insulating layer comprises at least one groove in the encapsulation area. At least one of the plurality of wires comprises a first portion in the display area and a second portion within a corresponding groove of the encapsulation area. There is only one said second portion present in each groove.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: July 27, 2021
    Inventors: Liangliang Liu, Feng Kang, Nini Bai, Qi Liu
  • Patent number: 11069640
    Abstract: A package for power electronics includes a power substrate, a number of power semiconductor die, and a Kelvin connection contact. Each one of the power semiconductor die are on the power substrate and include a first power switching pad, a second power switching pad, a control pad, a semiconductor structure, and a Kelvin connection pad. The semiconductor structure is between the first power switching pad, the second power switching pad, and the control pad, and is configured such that a resistance of a power switching path between the first power switching pad and the second power switching pad is based on a control signal provided at the control pad. The Kelvin connection pad is coupled to the power switching path. The Kelvin connection contact is coupled to the Kelvin connection pad of each one of the power semiconductor die via a Kelvin conductive trace on the power substrate.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: July 20, 2021
    Assignee: Cree Fayetteville, Inc.
    Inventors: Brice McPherson, Daniel Martin, Jennifer Stabach
  • Patent number: 11069565
    Abstract: A semiconductor interconnect structure and its manufacturing method are presented. The manufacturing method includes: providing a substrate structure, wherein the substrate structure comprises: a substrate; a first metal layer on the substrate; a dielectric layer on the substrate, wherein the dielectric layer covers the first metal layer, and wherein the dielectric layer has a hole extending to the first metal layer; and a hard mask layer on the dielectric layer; removing the hard mask layer on the dielectric layer; selectively depositing a second metal layer at the bottom of the hole; and depositing a third metal layer, wherein the third metal layer fills the hole. This semiconductor interconnect structure provides improved reliability over conventional structures.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: July 20, 2021
    Inventor: Jiquan Liu
  • Patent number: 11056467
    Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Duesman, James E. Davis, Warren L. Boyer
  • Patent number: 11043730
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die surrounded by a first molding compound layer. A redistribution layer (RDL) structure is formed on a non-active surface of the semiconductor die and the first molding compound layer. A second molding compound layer is formed on the RDL structure. An insulating capping layer covers the second molding compound layer. An antenna is electrically coupled to the semiconductor die and includes a first antenna element formed in the RDL structure and a second antenna element formed between the second molding compound layer and the insulating capping layer.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: June 22, 2021
    Assignee: MediaTek Inc.
    Inventors: Nai-Wei Liu, Yen-Yao Chi, Tzu-Hung Lin, Wen-Sung Hsu
  • Patent number: 11037819
    Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh
  • Patent number: 11031578
    Abstract: The present disclosure discloses a display substrate and a manufacturing thereof. The display substrate comprises a base substrate, a pixel defining layer formed on the base substrate, wherein the pixel defining layer is provided with an opening region comprising a bottom wall and at least one sidewall, wherein in the opening region, an edge of the bottom wall is provided with at least one hydrophilic inducing column, wherein at least one of the hydrophilic inducing column has a hydrophilic surface.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 8, 2021
    Inventors: Dejiang Zhao, Yimin Chen
  • Patent number: 11024596
    Abstract: [Problem] To bond an electronic component on a substrate via an adhesive material satisfactorily. [Solution] A bonding device 10 for thermally bonding an electronic component 100 to a substrate 110 or to another electronic component via an adhesive material 112, the bonding device being provided with: a bonding tool 40 comprising a bonding distal-end portion 42 which includes a bonding surface 44 and tapered side surfaces 46 formed in a tapering shape becoming narrower toward the bonding surface 44, the bonding surface 44 having a first suction hole 50 for suction-attaching the electronic component 100 via an individual piece of a porous sheet 130, the tapered side surfaces 46 having second suction holes 52, 54 for suction-attaching the porous sheet 130; and a bonding control unit 30 which controls the first suction hole 50 and the second suction holes 52, 54 independently from each other.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 1, 2021
    Assignee: SHINKAWA LTD.
    Inventors: Osamu Watanabe, Tomonori Nakamura, Toru Maeda, Satoru Nagai, Yuichiro Noguchi
  • Patent number: 11024656
    Abstract: An active matrix substrate in which step-caused disconnection of a metal film in a contact hole does not easily occur includes a first to third insulating films and first to third metal films on a glass substrate and a contact hole electrically connecting the first and second metal film, the contact hole including first to third hole present respectively in the first to third insulating films, the first and third metal films being in contact with each other inside the first hole, the second insulating film and an oxide semiconductor film overlapping with each other in a region below the third hole, the second and third metal films being in contact with each other in a region above the first insulating film and either inside or below the third hole.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: June 1, 2021
    Inventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Yaneda
  • Patent number: 11024561
    Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: June 1, 2021
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Il Kwon Shim, Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Yu Gu
  • Patent number: 11018028
    Abstract: An applying method includes the following steps. Firstly, a conductive adhesive including a plurality of conductive particles and an insulating binder is provided. Then, a carrier plate is provided. Then, a patterned adhesive is formed on the carrier plate by the conductive adhesive, wherein the patterned adhesive includes a first transferring portion. Then, a manufacturing device including a needle is provided. Then, the needle of the manufacturing device is moved to contact the first transferring portion. Then, the transferring portion is transferred to a board by the manufacturing device.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: May 25, 2021
    Assignee: Epistar Corporation
    Inventor: Min-Hsun Hsieh
  • Patent number: 11011488
    Abstract: A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: May 18, 2021
    Inventors: Nazila Dadvand, Christopher Daniel Manack, Salvatore Frank Pavone