Abstract: A system and method of preventing pattern lifting during a trench etch/clean process is disclosed. A first layer comprising a first dip is formed over a first via pattern. A trench resist layer is formed. The trench resist layer is patterned with a trench reticle to produce a second via pattern in the trench resist layer over the first via pattern. A photo resist over the first via pattern is opened during a trench processing. Thus, an additional pattern added on a trench pattern reticle is used to open, i.e., remove resist over, a huge via feature area causing under layer dip.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice. Various platforms can be used to physically implement such a quantum computer. Platforms include an optical lattice, a Josephson junction array, a quantum dot, and a crystal structure. Each platform comprises an appropriate array of associated sites that can be used to approximate a desired Kagome geometry. A charge controller is desirably electrically coupled to the platform so that the array may be manipulated as desired.

Abstract: A semiconductor device, comprises: a wiring formed on a first insulating film, a second insulating film formed on the first insulating film and on the wiring, a contact hole formed in the second insulating film and located on the wiring, a coating that covers a sidewall of the contact hole and is formed by sputtering the wiring at the bottom of the contact hole, a barrier film formed on the coating and at the bottom of the contact hole, and an electrical conductor deposited in the contact hole.

Abstract: A system and method are disclosed for providing a fully self aligned bipolar transistor using modified cavity formation to optimize selective epitaxial growth. A collector of a transistor is formed and at least two layers of silicon oxide are formed above the collector and covered with a polysilicon external raised base. Then an emitter window is etched through the polysilicon external raised base down to the top layer of silicon oxide. A wet etch process is performed to form a cavity in the at least two layers of silicon oxide. Different wet etch rates of the silicon layers with respect to the wet etch process cause the cavity to be formed with a shape that optimizes selective epitaxial growth in the cavity. Polysilicon rich corners and a monocrystalline silicon base are then formed within the cavity.

Abstract: In the present invention, an etching hole 21 is formed in a polysilicon film 14 as a cavity-wall member. Through the etching hole 21, hydrofluoric acid is injected, so as to dissolve a silicon oxide film 13, thereby forming a cavity 22. In the cavity 22, a detecting unit 12 of a sensor is in an exposed condition. Next, by sputtering, an Al film 16 is deposited in the etching hole 21 and on an upper face of a substrate. Thereafter, a portion of the Al film 16 positioned on the polysilicon film 14 is removed by etching back, thereby leaving only a metal closure 16a of Al which closes the etching hole. The sputtering step is performed under a pressure of 5 Pa or less, so that the pressure in the cavity can be held to be low.

Abstract: A method for manufacturing a semiconductor device wherein both the threshold voltages of an N-type MISFET and a P-type MISFET are low, device can be easily manufactured at a lower cost and a higher product yield, and the reliability of the gate insulation film is higher. The gate insulation film is formed on the surface of a silicon substrate 1 in N-type MISFET forming region and the P-type MISFET forming region, and metal gates 4 and 5 are provided thereon. The metal gate 4 is made from a TiCoN film, and the work function thereof is set at 4.0 to 4.8 eV suited to the gate electrode material of the N-type MISFET. The metal gate 5 is formed from a portion of the TiCoN film by ion-implantation of oxygen into the TiCoN film configuring the gate electrode 4 at a dosage of 1013 to 1014 (ions/cm2) to raise the work function by around 0.2 to 0.8 eV.

Abstract: A mask layer is applied to a surface of a semiconductor structure or a seed layer deposited on the surface. The mask layer has a submicron width opening with a high aspect ratio that exposes a portion of the surface or seed layer. Conductive material is conformed to the opening, for example by plating, to form a first contact on the surface or seed layer. The mask and the top layer of the semiconductor structure, except for the portion under the first contact, are removed to expose a second layer of the semiconductor structure. An insulating layer is formed along the sidewalls of the first contact and the top layer of the semiconductor structure beneath the first contact. A mask is then applied to the second layer and a second contact is formed by selectively depositing metal only on the portion of the second layer exposed by the opening.

Abstract: A method for manufacturing a circuit board (7); in which, an electronic component is injected into a resin substrate at a low temperature, and then the resin substrate is improved in its heat withstanding property. The manufacturing method comprises the steps of softening by heat a resin substrate which contains a thermoplastic component and a chemical cross-link component and then injecting an electronic component (1) into the resin substrate; curing the resin substrate by bridging the chemical cross-link component of the resin substrate, making the resin substrate into a heat-withstanding substrate (70); and forming an electric wiring pattern (6) on the heat-withstanding substrate (70) for connection with a protruding electrode (2) of the electronic component (1). The circuit board (7) maintains the high dimensional accuracy throughout the manufacturing process. Thus, the present invention offers a superior circuit board, which is thin and compact in size and has a small thermal deformation rate.

Abstract: A method of manufacturing an image sensor, which avoids corroding a pad electrode with overexposure to corrosive chemicals, includes forming a pad electrode over a semiconductor substrate, forming a passivation layer over the pad electrode, applying a photoresist over the passivation layer, etching the photoresist and passivation layer to form a via hole exposing the pad electrode, and applying an amine based chemical for a predetermined, limited time to remove the photoresist. Alternatively, an amide based chemical which does not corrode the pad electrode can be substituted for the amine based chemical.

Abstract: A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.

Abstract: A method of depositing nanocrystalline diamond film on a substrate at a rate of not less than about 0.2 microns/hour at a substrate temperature less than about 500° C. The method includes seeding the substrate surface with nanocrystalline diamond powder to an areal density of not less than about 1010sites/cm2, and contacting the seeded substrate surface with a gas of about 99% by volume of an inert gas other than helium and about 1% by volume of methane or hydrogen and one or more of acetylene, fullerene and anthracene in the presence of a microwave induced plasma while maintaining the substrate temperature less than about 500° C. to deposit nanocrystalline diamond on the seeded substrate surface at a rate not less than about 0.2 microns/hour. Coatings of nanocrystalline diamond with average particle diameters of less than about 20 nanometers can be deposited with thermal budgets of 500° C.-4 hours or less onto a variety of substrates such as MEMS devices.

Abstract: A method for forming a surface strap includes forming a deep trench capacitor having a conductive connection layer on its surface in the substrate and the conductive connection layer in contact with the conductive layer; forming a poly-Si layer covering the pad layer and the conductive connection layer; performing a selective ion implantation with an angle to make part of the poly-Si layer an undoped poly-Si layer; removing the undoped poly-Si layer to expose part of the conductive connection layer; etching the exposed conductive connection layer to form a recess; removing the poly-Si layer to make the exposed conductive connection layer a conductive connection strap; filling the recess with an insulation material to form a shallow trench isolation; exposing the conductive layer; and selectively removing the conductive layer to form a first conductive strap which forms the surface strap together with the conductive connection strap.

Abstract: A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

Abstract: A method for manufacturing a semiconductor device including providing a semiconductor substrate including a cell area formed with relatively high device element density and a scribe line area formed with a device element density lower than the device element density of the cell area. An insulating layer is deposited over the semiconductor substrate. The insulating layer is planarized through a chemical mechanical polishing (CMP) process including a first polishing step and a second polishing step having different removal rates with respect to the insulating layer formed over the cell area and the scribe area.

Abstract: Methods of forming a silicon carbide semiconductor device are disclosed. The methods include forming a semiconductor device at a first surface of a silicon carbide substrate having a first thickness, and mounting a carrier substrate to the first surface of the silicon carbide substrate. The carrier substrate provides mechanical support to the silicon carbide substrate. The methods further include thinning the silicon carbide substrate to a thickness less the first thickness, forming a metal layer on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate, and locally annealing the metal layer to form an ohmic contact on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate. The silicon carbide substrate is singulated to provide a singulated semiconductor device.

Abstract: A polysilicon liquid crystal display (LCD) device having a large width channel includes a buffer layer formed on a substrate, an active layer formed on the buffer layer and having a plurality of heat releasing parts, a gate line formed in a width direction of the active layer, at least one heat releasing path formed in each of the plurality of heat releasing parts, source and drain electrodes symmetrically formed at both sides of the active layer, and a contact hole connecting the source and drain electrodes and the active layer.

Abstract: A semiconductor device having a trench in the side portion of a conducting line pattern and methods of forming the same. The semiconductor device provides a way of preventing an electrical short between the conducting line pattern and a landing pad adjacent to the conducting line pattern. There are disposed two conducting line patterns on a semiconductor substrate. Each of the conducting line patterns includes a conducting line and a conducting line capping layer pattern stacked thereon. Each of the conducting line patterns has a trench between the conducting line capping layer pattern and the conducting line. Conducting line spacers are formed between the conducting line patterns. One conducting line spacer covers a portion of a sidewall of one of the conducting line patterns, and the remaining conducting line spacer covers an entire sidewall of the remaining conducting line pattern. A landing pad is disposed between the conducting line patterns.

Abstract: The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms.

Abstract: An electronic device (ICD) comprises a signal ground contact (LD1) for coupling the electronic device to signal ground, a die pad, and an integrated circuit. The die pad (DPD) is provided with a protrusion (PTR3) that is electrically coupled to the signal ground contact. The integrated circuit (PCH) has a contact pad (GP2) that faces the protrusion of the die pad and that is electrically coupled thereto.

Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.