Abstract: The centralized bus arbitration circuit 20 shown here allows processor 12-18 access to a bus 10 for a period of time determined by either the processor 12-18 or the circuit 20, as appropriate. Indefinite access and immediate return of control to the bus arbitration circuit 20 are also provided for.

Abstract: A LOCATE search dynamically locates resources (e.g., logical units (LUs) and transaction program and files associated with LUs) in a computer network so that a session can be established between the origin and the destination of the search.In a network which includes end nodes associated with server nodes, a resource contained in any node is located by a requesting node. The requesting node initiates a search of the resources residing within itself. If the resource does not reside in the requesting node, the server node searches the resources known to the server node that reside anywhere in the nework. If the resource is not known by the server node, it searchers all resources that reside in its associated end nodes. If the resource does not reside in the associated end nodes, either a request is sent to a central directory if one exists or a search of all resources in the network is made.

Abstract: An error supervision circuit for a non-encoded binary bit stream running through an elastic store comprising a memory having n locations, the bit rate of the stream supplied to the input of the memory differing from the bit rate of the stream produced at the output thereof. The successive bits in each group of n bits of the input stream are respectively written into the respective memory locations by write clock pulses supplied by a write register, at the input rate, and are successively read out from such locations by read clock pulses supplied by a read register at the output rate. The higher rate register is periodically interrupted for one or more bit periods to equalize filling and emptying of the memory. The bit streams at the input and output of the memory are supplied to respective data inputs of a comparator. A clock output of the lower rate register is connected to a first control input of the comparator to intermittently open a time window therein for receiving n bits of the lower rate bit stream.