Abstract: A sequential decoder for use in broadband mobile communications and a receiver including the sequential decoder. The sequential decoder computes likelihood values by referring to histories of paths to reduce the required computational effort. The paths include signal points having small tap coefficient values in an equalizer with a transversal filter, and may also include paths within a constraint length which are old in time.

Abstract: To provide a receiver not requiring any large circuit. A carrier-wave-phase-error table 15-1A for BPSK modulation in which a range equal to or more than 0 of I-axis is defined is prepared for a carrier-wave regenerating circuit 10A of a demodulating circuit 1A for orthogonally detecting a received signal in which digital signals according to BPSK, QPSK, and 8PSK modulations are time-multiplexed and outputting I and Q symbol-stream data It and Qt for each symbol.

Abstract: A desired signal and at least one interfering signal are joint demodulated with a Viterbi equalizer having an adaptive total number of states. The total number of states is based on channel impulse response (CIR) coefficients associated with the desired signal and the at least one interfering signal.

Abstract: A first transceiver transmits a set of test levels to a second transceiver through a communication channel with one or more types of companding laws. The second transceiver determines line encoding with, and conversion between, the companding laws present in the communication channel based on the received set of test signals. The set of test levels are signals having levels determined based on the difference between the normalized amplitude, vertex, or energy curves for the types of companding laws, with or without accounting for other sources of network distortion. Additional distortion from line characteristics, such as robbed-bit signaling (RBS) and/or line impairment, may be detected based on changes in encoding sample levels of transmitted test signals that are reconstructed by the second transceiver. The second transceiver may then transmit information to the first transceiver about the companding laws and other sources of distortion present in the network.

Abstract: A method for convolutive encoding process and transmission by packets of a digital data series in which a set of successive n=K−1 bits are discriminated to form a current word of n bits. A stable starting binary value for the convolution encoding is defined and the current word is subjected to a convolutive encoding of depth K, at each bit value i(k) corresponding thus an encoded symbol S(k)={a(k);b(k)}. A packet of encoded symbols is formed by concatenating the encoded symbols and the stable constraint value is assigned to the convolutive encoding at the packet end. An encapsulation message the packet of encoded symbols is generated and the encapsulation message and packet of encoded symbols are transmitted in the same message for decoding and use. Decoding of the encoded symbols takes place in relation to the encapsulation message value and packet of encoded symbols length.

Abstract: Receiver module and receiver formed from several cascaded modules. The module comprises inputs (E1, E2, E3, E4) and outputs (S1, S2, S3, S4) connected to selection means (44), to switching means (45) and to decoding means (46, 58, 60). Such modules can be cascaded by simply connecting the corresponding inputs and outputs. The final module delivers the transmitted information. Application to differential phase modulation and orthogonal modulation spread spectrum digital transmission.

Abstract: A mixed-signal-controlled phase-locked loop is provided. This loop includes a mixed-signal-controlled oscillator circuit for generating an oscillating signal having an oscillating frequency and a phase in response to a digital control signal and an analog control signal, a phase-frequency detector circuit electrically connected to the mixed-signal-controlled oscillator circuit, detecting the phase and the oscillating frequency of the oscillating signal and comparing the phase and the oscillating frequency with those of a reference signal to generate an error signal after the phase and oscillating frequency are detected, and a mixed-control-signal-producing circuit electrically connected to the mixed-signal-controlled oscillator circuit and the phase-frequency detector circuit for receiving the error signal to output the analog control signal and the digital control signal to the mixed-signal-controlled oscillator circuit.

Abstract: Methods and apparatus for performing gain control in a manner that is designed to maximize the use of the dynamic range of signal processing circuitry, e.g., an A/D converter, while minimizing signal clipping are described. In one embodiment a power reference level used for automatic gain control purposes is periodically adjusted. An exemplary state machine of the present invention has an analysis state which collects signal statistics, e.g., signal clipping and threshold statistics, for a period of time corresponding to a fixed number of samples. During the analysis state, the number of samples that equal or exceed either the minimum or maximum valid values (e.g., clip points), supported by the signal processing circuitry, are accumulated. Statistics are also accumulated on the number of data samples that exceed thresholds, e.g., +/−tail thresholds, corresponding to points near the outer portion of the range supported by the signal processing circuitry.

Abstract: A method and apparatus for maximal-ratio combining of received frame data is provided. This technique increases the reliability of a communication network that includes multiple independent receivers. For example, when multiple independent receivers are not in agreement as to the received frame data (501, 502, 503), an embodiment of the invention provides a higher likelihood of correctly identifying the received frame data (501, 502, 503). A technique for determining a signal-to-noise ratio from a metric signal (504) derived from a decoder (701) in a receiver is provided. The signal-to-noise ratio may be characterized according to a polynomial estimate or stored in lookup table. The signal-to-noise ratio is used to apply a weighting (805) to “hard decision” data from the receiver to yield a weighted value (806). The weighted value is combined with weighted values from other receivers. The combined weighted values are applied to a data slicer (414) to yield received data (807).

Abstract: A system for repeating an xDSL signal (14) is disclosed. The system comprises a receiver (16) operable to receive the xDSL signal (14), a first analog front end (18) coupled to the receiver (16) and operable to convert the xDSL signal to a digital signal, and a series of digital signal processors (20, 22) coupled to the first analog front end (18) and operable to remove noise elements from the digital signal. Also provided is a second analog front end (24) coupled to the second digital signal processor (22) and operable to convert the digital signal back to the analog domain. A driver circuit (26) is operable to increase the signal strength of the analog signal and retransmits it over a new length of wiring.

Abstract: In a conventional correlation circuit for spread spectrum communication, when a sliding correlator is used, much time is required. When a matched filter is used, a problem is that a circuit scale and power consumption are increased. In the present invention, however, there is provided a correlation circuit for spread spectrum communication which minimizes the number of constituting elements, and can reduce the power consumption. In the correlation circuit for spread spectrum communication of the present invention, a spread spectrum received signal is A/D converted and accumulated in a data memory unit by a symbol unit, data rate is converted, and a high-rate MF performs a product sum operation processing at a high rate so that a correlation output is obtained.

Abstract: In a low power consumption data transmission circuit and method, and a liquid crystal display apparatus using the same, 24-bit display data is transmitted from a transceiver circuit to a receiver circuit through a transmission line so that the display data is displayed on a liquid crystal panel. The transceiver circuit has a holding circuit including an 8-stage shift register. The transceiver circuit outputs 24-bit data to the transmission line by use of first and second output circuits when data different from data held in the holding circuit is to be transmitted from the transmission line and outputs data indicative of a hold position in the holding circuit from the second output circuit when the same data as that held in the holding circuit is to be transmitted from the transmission line.

Abstract: An equalization method and apparatus for equalizing a plurality of input signals received on a multichannel link leverages shared equalization resources to generate dedicated tap coefficients for application to the signals and updates the dedicated tap coefficients upon measured degradation in the quality of the signals. The equalization method and apparatus achieves acceptable bit error rates with relatively low overhead.

Abstract: An equalizer with a phase-locked loop comprising: a phase rotator which rotates a phase of a received signal to output a rotated signal; an impulse response detector which detects impulse responses of a transmission line through which the received signal has been transmitted on the basis of the rotated signal; a first region designator which designates a first region on the basis of the impulse responses; a second region designator which designates a second region on the basis of the impulse responses; an equalizer which estimates a sequence on the basis of the rotated signal by using the impulse responses in the first region; a replica generator which generates a replica of the received signal on the basis of the sequence by using the impulse responses in the second region; a phase detector which detects a phase difference between the replica and the rotated signal; and a circuit for controlling the phase rotator on the basis of the phase difference to decrease the phase difference.

Abstract: The present invention relates to a demodulator provided to extract two signals modulated in phase quadrature from an intermediary frequency signal, including two analog-to-digital converters receiving the intermediary frequency signal and clocked in phase opposition by a clock at a frequency smaller than the intermediary frequency, at least equal to the bandwidth of the modulated signals, and such that the central frequency of one of the aliased spectrums of the signal converted into digital is substantially equal to half the clock frequency; and two multipliers respectively receiving the outputs of the analog-to-digital converters and receiving at the same time a sequence of values 1, −1, 1, −1, 1 . . . at the clock rate.

Abstract: A narrow-band bandpass filter is implemented in a field programmable gate array (FPGA). An analog-to-digital converter quantizes an input analog signal with a high degree of precision to produce input data samples. A sigma-delta modulator re-quantizes the samples with a substantially lower degree of precision. The re-quantized samples are passed through a bandpass, lowpass, or highpass, finite impulse response (FIR) filter which operates at the lower degree of precision. The reduced degree of precision enables a substantial reduction in the number of resources required to implement the narrow-band bandpass, lowpass, or highpass filter in the FPGA. The modulator includes a predictor filter which has a center frequency coinciding with that of the FIR filter, and redistributes noise such that it is lowest within the passband of the FIR filter. The narrow-band filter design can be adapted to incorporate a single or multi-rate decimator configuration.

Abstract: A system for increasing data transmission capacity over a wireless mobile link while at the same time providing improved jamming resistance utilizes discrete trellis-coded modulation involving frequency hopping individual symbols, along with encoding the phase of a symbol as a frequency offset to the hopped carrier frequency. This modulation system permits coherent demodulation in which both phase and amplitude of a symbol is robustly decoded and in which each phase of a quadrature amplitude modulated signal is decoded by the detected frequency offset, thus to provide reliable recovery of phase in the demodulation section. The resulting system improves spectrum efficiency and permits fast frequency hopping for improved jamming resistance, with the utilization of frequency offset coding permitting the coherent demodulation that improves the error-rate without the introduction of additional reference bits.

Abstract: A partial response maximum likelihood (PRML) bit detection apparatus derives a bit sequence from an input information signal. The apparatus includes: input apparatus for receiving the input information signal; sampling apparatus for sampling the input information signal at sampling instants so as to obtain samples of the input information signal at the sampling instants; conversion apparatus for converting an array of the samples into an array of bits of a first or a second binary value, detection apparatus for repeatedly detecting a state for subsequent sequences of n subsequent bits of the array of bits, the subsequent sequences being obtained by shifting a time window of n subsequent bits each time over one bit in time; apparatus for establishing the best path through the states; and deriving apparatus for deriving a sequence of bits in accordance with the best path through the states.

Abstract: A hybrid modem or transceiver includes communication hardware that transforms time domain samples of a received signal to frequency domain information. The communication hardware transfers the frequency domain information to a host computer which executes receiver software to process the frequency domain information and extract data. The host computer also executes transmitter software to determine frequency domain information corresponding to a transmitted signal. The transmitter software transfers that frequency domain information to the communication hardware which converts the frequency domain information to time domain samples of the transmitted signal. Typically, the hybrid modem or transceiver includes processing hardware for Fourier transforms and inverse Fourier transforms that convert information between the time and frequency domains.

Abstract: Method measures imperfections in digital quadrature modulator and demodulator operation, and to a digital quadrature modulator/quadrature demodulator. The modulator includes means for modulating quadrature-phase I and Q input signals to generate an output signals to generate an output signal including quadrature-phase I and Q components; means for taking momentary amplitude samples from the output signal of the modulator at a rate based on a symbol clock of the modulator; means for classifying a direction angle of the symbol to be modulated at a particular time into a particular direction angle sector; means for linking the amplitude samples of the output signal to the direction angle sector corresponding to the symbol to be transmitted at a particular time, and means for comparing amplitudes of samples belonging to each direction angle sector with other direction angle sectors or with an ideal value for determining imperfections of the output signal of the modulator.